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Siemens ERTEC200 Manual
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Siemens ERTEC200 Manual

Siemens ERTEC200 Manual

Enhanced real-time ethernet controller
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E
RTEC 200
E
nhanced Real-Time Ethernet Controller
Manual
Page 1
Copyright © Siemens AG 2007. All rights reserved.
ERTEC 200 Manual
Technical data subject to change
Version 1.1.0

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Summary of Contents for Siemens ERTEC200

  • Page 1 RTEC 200 nhanced Real-Time Ethernet Controller Manual Page 1 Copyright © Siemens AG 2007. All rights reserved. ERTEC 200 Manual Technical data subject to change Version 1.1.0...
  • Page 2 All product and system names are registered trademarks of their respective owner and must be treated as such. Technical data subject to change. Page 2 Copyright © Siemens AG 2007. All rights reserved. ERTEC 200 Manual Technical data subject to change Version 1.1.0...
  • Page 3 Section 12 List of terms and references Scope of the Manual This manual applies to the following product: ERTEC 200 Version 01 and higher Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Page 3 ERTEC 200 Manual...
  • Page 4 Federal Republic of Germany Technical Contacts for USA PROFI Interface Center: One Internet Plaza PO Box 4991 Johnson City, TN 37602-4991 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Phone: 0911/750-2736 Phone: 0911/750-2080 Fax: 0911/750-2100 E-mail: ComDeC@siemens.com Mailing address: P.O.

  • Page 5: Table Of Contents

    Address Assignment of Timer Registers... 40 4.3.4 Timer Register Description ... 40 4.4 F-Timer Function ... 43 4.4.1 Address Assignment of F-Timer Registers ... 44 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Page 5 ERTEC 200 Manual Version 1.1.0...
  • Page 6 7.2 Page Offset Setting ... 76 7.3 LBU Address Mapping ... 77 7.4 Page Control Setting ... 78 7.5 Host Access to the ERTEC200 ... 78 7.5.1 LBU Read from ERTEC 200 with separate Read/Write line (LBU_RDY_N active low) ... 79 7.5.2...
  • Page 7 11.2 Trace Interface ... 95 11.3 JTAG Interface ... 95 11.4 Debugging via UART... 95 Miscellaneous...96 12.1 Acronyms/Glossary: ... 96 12.2 References: ... 97 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Page 7 ERTEC 200 Manual Version 1.1.0...
  • Page 8 Table 33: Partitioning of Memory Areas ... 91 Table 34: Detailed Description of Memory Segments... 93 Table 35: Pin Assignment of JTAG Interface... 95 Page 8 Copyright © Siemens AG 2007. All rights reserved. ERTEC 200 Manual Technical data subject to change Version 1.1.0...

  • Page 9: Introduction

    The ERTEC 200 is intended for the implementation of PROFINET devices with RT and IRT functionality. With its integrated ARM946 processor and 2-port Ethernet switch with integrated PHYs and the option to connect an external host processor system to a local bus interface, it meets all the requirements for implementing PROFINET devices with integrated switch functionality.

  • Page 10: Structure Of The Ertec 200

    Master Input Input Decode MUX/Arb. stage stage Multi-Layer-AHB 50 MHz/32Bit MII-0 Figure 1: ERTEC 200 Block Diagram Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ARM946ES with ARM- I-Cache Interrupt- (8kByte) D-Cache Controller (4kByte) D-TCM...

  • Page 11: Ertec 200 Package

    /12/ Code description for soldering. When working with modules, always take precautionary measures against electrostatic charge (ESD – Electrostatic Sensitive Devices). Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Page 11 ERTEC 200 Manual Version 1.1.0...

  • Page 12: Signal Function Description

    GPIO16 SPI1_SSPCTL GPIO17 SPI1_SSPOE GPIO18 SPI1_SSPRXD GPIO19 SPI1_SSPTXD GPIO20 SPI1_SCLKOU GPIO21 SPI1_SFRMOU Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Alternative Pull- Function 3 (Reset) General Purpose I/O / I/O B/O/(I) B/O/(I) B/O/O/(I) B/O/O/(I) B/O/(I)

  • Page 13: Jtag And Debug

    I (I) 1.5.3 Trace Port Signal Name (Reset) TRACECLK B (O) Reserved I (I) Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Alternative Function 3 (Reset) General Purpose I/O / I/O B/I/O/(I) B/I/O/(I) B/I (I) B/O/(I)

  • Page 14: Clock And Reset

    1.5.6 EMIF (External Memory Interface) Signal Name Alternative Reset Function DTR_N BOOT0 OE_DRIVER_N Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Pull- Comment Quartz connection Quartz connection F_CLK for F-counter Tristate or reference clock output, 25 MHz...
  • Page 15 EMIF (External Memory Interface) BOOT1 BOOT2 BOOT3 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Pull- Comment (Reset) Address bit 13 O (O) SDRAM: Address 11 Address bit 14 O (O)

  • Page 16: Lbu, Mii Interface Or Etm Trace Interface

    LBU_A11 RXD_P23 LBU_A12 CRS_P2 LBU_A13 RX_ER_P2 LBU_A14 RX_DV_P2 LBU_A15 COL_P2 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Pull- (Reset) EMIF (External Memory Interface) O (O) O (O) O (O) O (O) O (O) O (O)
  • Page 17 TX_ERR_P1 LBU_D6 TXD_P20 LBU_D7 TXD_P21 LBU_D8 TXD_P22 LBU_D9 TXD_P23 LBU_D10 TX_EN_P2 LBU_D11 TX_ERR_P2 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Function 3 Function 4 (Reset ETM Trace Config GPIO[44:32] Reserved [6,5,2]) Config (6,5,2)=101b [6,5,2]=111b...

  • Page 18: Ethernet Phy1 And Phy2

    P2TxN P2TxP P2VSSATX2 P2RDxP P2RDxN P2TDxP P2TDxN P2SDxP P2SDxN VSSAPLLCB VDDACB VDDAPLL EXTRES Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Function 3 Function 4 (Reset ETM Trace Config GPIO[44:32] Reserved [6,5,2]) Config (6,5,2)=101b [6,5,2]=111b...

  • Page 19: Power Supply

    286-288 GND (PECL) 289-304 Not Used Pins Table 1: ERTEC 200 Pin Assignment and Signal Description Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Pull- PIN No. Power Supply D6, D9, D12, D18, E5, E13, E18, F6,...
  • Page 20 GPIO_PORT_MODE_H registers. The tabs are described in Section 4.2.2. The alternative LBU/MII functions are selected with the configuration pins CONFIG[6,5,2] in the user design. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Output Power supply...

  • Page 21: Arm946E-S Processor

    The processor system has an interface to the integrated AHB bus. Figure 3: Structure of ARM946E-S Processor System Copyright © Siemens AG 2007. All rights reserved. ERTEC 200 Manual Technical data subject to change...

  • Page 22: Description Of Arm946E-S

    For more information about the D-TCM refer to document /1/ Section 5. For more information on the description of the ARM946 registers, refer to Section 2.10 of this document. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ERTEC 200 Manual Version 1.1.0...

  • Page 23: Memory Protection Unit (Mpu)

    The interrupt controller is operated at a clock frequency of 50 MHz. Interrupt-request signals generated with a higher frequency must be lengthened accordingly for error-free detection. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ERTEC 200 Manual...

  • Page 24: Prioritization Of Interrupts

    During one or more accepted interrupts, the priority distribution of the IRQ/FIQ interrupt inputs must not be changed because the ICU can otherwise no longer correctly assign the EOI commands. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ERTEC 200 Manual Version 1.1.0...

  • Page 25: Irq Interrupt Sources

    (1) Access to non-existing addresses is detected by the individual function groups of the ERTEC 200 and triggers a pulse with duration Tp = 2/50 MHz. For evaluation of this interrupt, the connected FIQ input must be specified as an edge-triggered input. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change IRQ Interrupts...

  • Page 26: Irq Interrupts As Fiq Interrupt Sources

    0x005C ISREG 0x0060 TRIGREG 0x0064 EDGEREG 0x0068 SWIRREG 0x006C PRIOREG 0 0x0070 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change (Base Address 0x5000_0000) Address Area Access Default 4 bytes 0xFFFFFFFF 4 bytes 0xFFFFFFFF 4 bytes...

  • Page 27: 2.9.11 Icu Register Description

    Confirmation of highest-priority pending interrupt request by reading the associated interrupt vector Bit No. Name 3 – 0 IRVEC 31 - 4 Vector ID Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change 4 bytes 0x0000000F 4 bytes 0x0000000F Addr.: 0x5000_0000 Description For pending, valid interrupt: Binary code of input number.
  • Page 28 Indication of the fast interrupt requests confirmed by the CPU Bit No. Name 7 – 0 FIQISR Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x5000_0018 Description Binary code of FIQ number Valid FIQ vector: always ‘1’.
  • Page 29 (only if edge detection is specified for the associated input) Bit No. Name 15 – 0 EDGEREG Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x5000_0050 Description Inputs 0 to 7 of the FIQ interrupt controller...
  • Page 30 Specification of priority of an interrupt request at the associated input Bit No. Name 3 – 0 PRIOREG Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x5000_006C Description Interrupt input 0 to 15 0=No interrupt request 1=Set interrupt request Addr.: 0x5000_0070...

  • Page 31: 2.10 Arm946E-S Register

    When this register is written to, unforeseeable configuration changes can occur in the ARM946. Refer to documents /1/ and /2/ for a detailed description of the ARM946 registers. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...

  • Page 32: Bus System Of The Ertec 200

    In this case, the ARM master would have to pause in a “Wait” until the IRT master enables the EMIF slave again. To prevent this situation, monitoring is integrated into the IRT switch, which enables the slave momentarily via an IDLE state after 8 consecutive data transfers (burst or single access).

  • Page 33: O On Apb Bus

    Watchdog Reset • Software reset caused by setting the XRES_SOFT bit in the reset control register (system control register area) Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Wait States on the AHB Bit 7:0...

  • Page 34: Booting From External Rom

    4.1.3 Booting via UART Boot mode via UART uses a bootstrap method that first downloads to the ERTEC200 a routine for operating the serial interface, which then performs the actual download of the program. After the boot operation, the UART interface can be used in a different capacity (e.g., as a terminal interface).

  • Page 35: General Purpose I/O (Gpio)

    CONFIG[2] = 1. The GPIOs[44:32] can then be used as normal inputs or outputs. The direction of the GPIOs[44:32] can be programmed bit-by-bit in the "GPIO_IOCTRL2“ register. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...

  • Page 36: Address Assignment Of Gpio Registers

    GPIO1_PORT_MODE GPIO2_PORT_MODE GPIO3_PORT_MODE GPIO4_PORT_MODE 11:10 GPIO5_PORT_MODE 13:12 GPIO6_PORT_MODE 15:14 GPIO7_PORT_MODE Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change GPIO (Base Address 0x4000_2500) Address Area Access 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes...
  • Page 37 Description Output register for General Purpose IO [44:32] Bit No. Name 31..13 Reserved 12..0 GPIO2_OUT[44:32] Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Port GPIO[8]; Port GPIO[9]; Port GPIO[10]; Port GPIO[11]; Port GPIO[12]; Port GPIO[13];...

  • Page 38: Timer 0/1/2

    Normally, the timer clock operates at 50 MHz, which is generated by the internal PLL. Each timer can also be operated with an 8-bit prescaler. This can be used to increase the timer time accordingly. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2528...

  • Page 39: Timer 0/1 Interrupts

    When the level is 1, the timer value is reset to zero. Further operation of the timer and the interrupt generation are the same as in one-shot mode. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ERTEC 200 Manual Version 1.1.0...

  • Page 40: Address Assignment Of Timer Registers

    Reserved Status 31-6 Reserved Important note: The bits designated with *) are not applicable if the timers are cascaded! See CTRL_STAT1 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Timer (Base Address 0x4000_2000) Access Default...
  • Page 41 Remark about the prescalers: The current counter value of the prescalers cannot be read. In addition, there are no status bits for the prescalers indicating when the counter state is 0. The prescalers always run cyclically (in Reload mode). Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2004...
  • Page 42 Timer Register 2. Values of Timer 2. Bit No. Name 31:16 Reserved 15:0 Timer [15:0] Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2014 Description Reload value of prescaler 0 Reload value of prescaler 1 Not relevant (read=0) Addr.: 0x4000_2018...

  • Page 43: F-Timer Function

    Sync Stage: CLK_APB 3 stages + DIRECT_IN edge detect+ F-COUNTER-EN enable F_CLK Figure 5: Block Diagram of F-Counter Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change F_CLK 32-Bit Down-Counter Read: F-Counter-Val F-Counter-Val(31:0) APB-Bus Write: F-Counter-Res Reset...

  • Page 44: Address Assignment Of F-Timer Registers

    55AAh is entered in this register. Resets are thus possible via 16-bit and 32-bit accesses. Bit No. Name 31:16 F-CNT-RES[31:16] 15:0 F-CNT-RES[15:0] Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change F-Counter (Base Address 0x4000_2700) Access Default 4 bytes 0x00000000...

  • Page 45: Watchdog Timers

    X W D O U T 1 Z aeh l er 0 = 0 Figure 6: Watchdog Timing Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change T r i gger n L oesch en v on X W D O U T 0 d u r ch R u n /X St op _Z 0 ->...

  • Page 46: Watchdog Registers

    Name Run/xStop_V0 Run/xStop_Z1 Load(Trigger) Status_Counter 0 Status_Counter 1 15-5 Reserved 31-16 Key bits Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Watchdog (Base Address 0x4000_2100) Access Default 4 bytes 0x00000000 4 bytes 0x0000FFFF 4 bytes...
  • Page 47 Watchdog value 1. Value of watchdog counter 1. Bit No. Name 31-0 WDOG1[36:4] Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2104 Description Reload value for bits 15:0 of watchdog counter 0. Key bits for writing to this register (read=0).

  • Page 48: Uart Interface

    FIFO does not indicate the fill level. Because the DMA controller is only a single-channel controller, only send or receive control can take place via the DMA controller. The other channel must be controlled via software. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...

  • Page 49: Address Assignment Of Uart Registers

    UARTILPR 0x0020 0x0024 - 0x003C 0x0040 - 0x0098 0x009C - 0x00FF Table 14: Overview of UART Registers Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change UARTCLK BAUDDIV = (-----------------------------) - 1 BR x 16 BAUDDIV...

  • Page 50: Uart Register Description

    NOTE: When new data are displayed, the UARTDR data register must be read out first and then the UARTRSR error register. The error register is not updated until the data register is read. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2300...
  • Page 51 UARTLCR_H must be written at the end following the change. Example: Write UARTLCR_L and/or UARTLCR_M, write UARTLCR_H as acceptance. Write UARTLCR_H only means write and accept UARTLCR_H bits. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2308 Description Send break = 1 A LOW level is sent continuously at the Transmit output.
  • Page 52 BUSY RXFE TXFF RXFF TXFE Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2314 Description UART Enable = 1 UART sending/receiving of data is enabled SIR enable = 1 IrDA SIR Endec is enabled. The bit can only be changed if...
  • Page 53 UARTCLK ILPDVSR = ---------------------- - 1 IrLPBAUD16 Zero is not a valid divisor. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_231C Description Modem Interrupt Status This bit is set if UARTMSINTR is active.

  • Page 54: Synchronous Interface Spi

    Both interrupts are available on the IRQ interrupt controller of the ARM946E-S. The SPI module can be operated by the ARM946 or the internal DMA controller. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change SSPTXD...

  • Page 55: Address Assignment Of Spi Register

    0x0018 - 0x003C 0x0040 - 0x0090 0x0094 - 0x00FF Table 15: Overview of SPI Registers Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change (CPSDRV = 254, SCR = 255) to (CPSDRV = 2, SCR = 0)

  • Page 56: Spi Register Description

    SSPCR1 Description Control register 1. Configuration frame format and baud rate for SPI. Bit No. Name RORIE Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2200 Description 0000 Reserved (undefined) 0001 Reserved (undefined) 0010 Reserved (undefined)
  • Page 57 SPI clock prescale register Bit No. Name 7 - 0 CPSDVSR 15-5 ------------ Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Reserved Read: Value is undefined Write: Should always be written with zero Addr.: 0x4000_2208 Description...

  • Page 58: System Control Register

    ERTEC 200_TAG 0x0058 PHY_CONFIG 0x005C PHY_STATUS 0x0060 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2214 Description SPI Receive FIFO service request interrupt status 0 = SSPRXINTR is not active 1 = SSPRXINTR is active...

  • Page 59: System Control Register Description

    Only the bit of the last reset event occurrence is set. The two other bits are reset. Bit No. Name 31..3 Reserved HW_RESET SW_RESET WD_RESET Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change 4 bytes 0x00000000 Addr.: 0x4000_2600 Description ERTEC 200 identifier: 4027h HW release: 01h Metal fix: 00h Addr.: 0x4000_2604...
  • Page 60 Control signals of an incorrect addressing on the multi-layer AHB Bit No. Name 31:7 Reserved HBURST HSIZE HWRITE Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2614 Description Reserved INT_MASK_LOSS: Interrupt masking for INT_LOSS_STATE 0: Interrupt is enabled...
  • Page 61 AHB master lock enable. Master-selective enable of AHB lock functionality. Bit No. Name 31:4 Reserved Reserved Reserved Reserved Reserved Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2630 Description Reserved ARM946 Addr.: 0x4000_2634 Description Address Addr.: 0x4000_2638...
  • Page 62 Bit No. Name 31:17 PHY_RES_SEL 15 :14 P2_AUTOMDIXEN If CONFIG(6,5,2)=“111“ Bit not writeable, fix to default value. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x4000_2650 Description Reserved BIGENDIAN (read only) DisableGateTheClk: 1: ARM9 processor clock runs freely 0: ARM9 processor clock is paused by a Wait-for-Interrupt.
  • Page 63 P1/2_PHYENABLE = 1 triggers a reset extension internally in PHY beyond 5.2 ms. During this time, the PLL and all analog and digital components are powered up. The ready to operate status is signaled in the PHY_Status-Register with P1/2_PWRUPRST = 1. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change 000:...

  • Page 64: General Hardware Functions

    CONFIG[4:3]: CONFIG4, CONFIG3 = 00 CONFIG4, CONFIG3 = 01 CONFIG4, CONFIG3 = 10 CONFIG4, CONFIG3 = 11 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change CLOCK SOURCE 50/100/150 MHz (scalable) JTAG-Clock...

  • Page 65: Jtag Clock Supply

    Communication from the debugger via the JTAG interface is not possible during this time. The following figure shows the power-up phase of the PLL after a reset. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Connection of external PHYs...

  • Page 66: Hardware Reset

    IRT Switch Reset The switch module can be reset by means of a register in the IRT switch. The reset function of the switch module is retained until the bit is revoked again. The internal PHYs can be reset either via the RESET_N pin or by the IRT switch controller via PHY_RES_N.

  • Page 67: Address Space And Timeout Monitoring

    Select 50/100/150 Mhz clock frequency for ARM946E-S CONFIG[6,5] If LBU is disabled: PHY debug, GPIO[44:32], select ETM9 on LBU port Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change e and an FIQ2 interrupt egal accesses, and DMA, LBU).

  • Page 68: Table 18: Configurations For Ertec 200

    Config Config Config Table 18: Configurations for ERTEC 200 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Config Config Config REF_CLK tristate REF_CLK output (25 MHz) LBU = On, LBU-CFG: LBU_WR_N has read/write control LBU = On,...

  • Page 69: External Memory Interface (Emif)

    2 SDRAM refresh operations. Failure to do so can cause some refresh operations to be lost. Note that 32-bit access to blocks that are 8 bits wide requires 4 access attempts. During this time, the SDRAM cannot be refreshed. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...

  • Page 70: Address Assignment Of Emif Registers

    Async wait cycle config Description Async wait cycle config register Bit No. Name Reserved 29..8 Reserved 7..0 MAX_EXT_WAIT Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change EMIF (Base Address 0x7000_0000) Access Default 4 bytes 0x00000100 4 bytes 0x40000080...
  • Page 71 The refresh counter is always on, even if SDRAM is not used. In this case, refresh_rate = 0x1FFF (maximum value) should be set to keep the load as small as possible. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x7000_0008...
  • Page 72 R_SU 12..7 R_STROBE 6..4 R_HOLD 3..2 Reserved 1..0 ASIZE Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x7000_0010 Addr.: 0x7000_0014 Addr.: 0x7000_0018 Addr.: 0x7000_001C Description Extend Wait Timing Mode 0: RDY_PER_N = asynchronous 1: RDY_PER_N = synchronous Extend Wait mode 0: RDY_PER_N = don’t care...
  • Page 73 All other settings cause malfunctions The Mode Register Set command is initiated by writing to the bit in the register SDRAM_Bank_Config[15:8]. (Register SDRAM_Refresh-Control[29] =1) Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x7000_0020 Description...

  • Page 74: Local Bus Unit (Lbu)

    (Wait) first. LBU_RDY_N will be active for a 50 MHz-Clock if data will be read or write. After that LBU_RDY_N switched back to tristate. The external Pull- (up/down) resistor drives the ready state. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...
  • Page 75 The four segments are addressed via the two LBU_SEG[1:0] inputs. LBU_SEG[1 : 0] Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addressed Segment LBU_PAGE0 LBU_PAGE1 LBU_PAGE2 LBU_PAGE3 ERTEC 200 Manual Version 1.1.0...

  • Page 76: Page Range Setting

    I/O. If access to this address area is no longer required after the initialization, the page can then be reassigned in order to access other address areas of the ERTEC 200. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...

  • Page 77: Lbu Address Mapping

    LBU_ADR [19:0] for this purpose. In addition, the addresses A[21:20] are necessary for the segment selection. These are connected to the LBU pins LBU_SEG[1:0]. Host Figure 12: Interconnection of Addresses between Host and ERTEC 200 LBU Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change SEGMENT SEGMENT...

  • Page 78: Page Control Setting

    Access by the host is asynchronous to the AHB clock of the ERTEC 200. For this reason, it is synchronized with the AHB clock. The following figures show different read- and write sequences with the timings: Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...

  • Page 79: Lbu Read From Ertec 200 With Separate Read/Write Line (Lbu_Rdy_N Active Low)

    Table 25: LBU Read access timing with seperate Read/Write line Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Description RCSH...

  • Page 80: Lbu Write To Ertec 200 With Separate Read/Write Line (Lbu_Rdy_N Active Low)

    Table 26: LBU Write access timing with seperate Read/Write line Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Description WCSH...

  • Page 81: Lbu Read From Ertec 200 With Common Read/Write Line (Lbu_Rdy_N Active Low)

    Table 27: LBU Read access timing with common Read/Write line Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Description 2 ns...

  • Page 82: Lbu Write To Ertec 200 With Common Read/Write Line (Lbu_Rdy_N Active Low)

    The ERTEC 200 generates 2 interrupt signals, LBU_IRQ0_N and LBU_IRQ1_N, to the external host. Both interrupts are generated in the IRT switch interrupt controller. Both signals are set by default to Low Active. However, they can also be assigned different parameters in the IRT switch.

  • Page 83: Address Assignment Of Lbu Registers

    LBU Register Description LBU_P0_RG_L LBU_P1_RG_L LBU_P2_RG_L LBU_P3_RG_L Description Low word of LBU Pagex_Range_register Bit No. Name 15..0 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Access Default 2 bytes 0x0000 2 bytes 0x0001 2 bytes 0x0000...
  • Page 84 LBU_P3_CFG Description Configuration for the individual pages Bit No. Name 15..1 PAGE_X_32 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: LBU_CS_R_N+0x02 Addr.: LBU_CS_R_N+0x12 Addr.: LBU_CS_R_N+0x22 Addr.: LBU_CS_R_N+0x32 Description Upper 16 bits for area setting...

  • Page 85: Dma-Controller

    When the DMA transfer is complete, a DMA_INTR interrupt takes place. In the case of a transfer to the UART or SPI, the interrupt takes place after the last byte is transferred. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change...

  • Page 86: Dma Register Address Assignment

    Description To define the data block length. 31..24 Reserved 23..21 D_DELAY_EXTENTI 20..16 S_DELAY_EXTENTI 15..0 BYTE_COUNT Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change DMA-Register (Start 0x8000_0000) Address Access Area 4 bytes 0x00000000 4 bytes 0x00000000...
  • Page 87 ****: When synchronization is used, the interrupt takes place only after the target request has been activated again. When D_Delay is used, the interrupt takes place only after the delay of the last write access. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Addr.: 0x8000_000C...

  • Page 88: Multiport Ethernet Phy

    Config port of the PHY. This configuration can be modified later in the PHY register set. The internal Config port comprises the following parameter assignment, which at present can be permanently set or set via software in the PHY_CONFIG system control register. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Description...
  • Page 89 If the Power-ON-reset is used, then the PHYs are active after the RESET phase. If the PHY_Reset_N is used, and the SMI module in the IRT switch has not been activated, then the PHYs remain in the reset state (no power loss from the PHYs).
  • Page 90 PHYs and the reference voltage placed on the EXTRES pin. All other inputs of the TX/FX interface must be connected to GND or VDD. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ERTEC 200 Manual Version 1.1.0...

  • Page 91: 10 Memory Description

    Only the ARM946E-S can access both address areas. IRT accesses to its own KRAM do not use the AHB bus. These accesses are implemented in the IRT switch controller. The KRAM can be addressed starting from the memory area 0x1010_0000. An access in the non-permissible register area is detected by an IRT-internal error signal and not by an AHB acknowledgement time-out error.

  • Page 92: 10.2 Detailed Memory Description

    Timer 0 - 2 Watchdog UART Reserved GPIO System control register block F counter Reserviert Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Größe Adressbereich After Reset: Boot-ROM (8kB physical.; memory swap=00b); After memory swap: EMIF-SDRAM (128MB physical.;...

  • Page 93: Table 34: Detailed Description Of Memory Segments

    N. In this case, the number of mirrorings N = 8. Access to the 4 unused bytes does not result in an acknowledgement timeout, but the read or written values are undefined. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Größe...

  • Page 94: 11 Test And Debugging

    The ETM registers are not described in this document because they are handled differently according the ETM version being used. For a detailed description, refer to /7/. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change (*1) ERTEC 200 Manual Version 1.1.0...

  • Page 95: Trace Interface

    IRQ interrupt sources of the UARTare mapped to the FIQs with numbers 6 or 7. This enables debugging of interrupt routines. Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Pin No.

  • Page 96: 12 Miscellaneous

    Pull Down Pull Up Real Time Standard Serial Peripheral Interface Soft Real Time Software UART Universal Asynchronous Receiver / Transmitter Warteschlange (queue) Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ERTEC 200 Manual Version 1.1.0...

  • Page 97: 12.2 References

    IEEE Standard Test Access Port and Boundary-Scan Architecture (1149.1 IEEE Boundary Scan 2001.PDF); /10/ IR35-107-3.pdf /11/ LeadfreeIR50_60.pdf /12/ Codeexpl.pdf /13/ PHY_Data_Sheet.pdf /14/ EB 200 Manual V1.1.0 (EB200_Manual_V110.PDF); Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change ERTEC 200 Manual Version 1.1.0...

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