Page 1 MVME172 VME Embedded Controller Programmer’s Reference Guide VME172A/PG2 Edition of February 1999...
Page 2 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Page 3 This manual provides board level information and detailed ASIC chip information including register bit descriptions for the MVME172 Embedded Controller. The information contained in this manual applies to the following MVME172 models: MVME172-303 MVME172-213 MVME172-313 MVME172-223 MVME172-323 MVME172-233 MVME172-333 MVME172-243...
Page 4 The status bit can be read by software to determine operational or exception conditions. This edition of the MVME172 VME Embedded Controller Programmer’s Reference Guide incorporates the following changes: The ‘‘MVME172 Version Register‘‘...
Page 5 The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1990, and may be used only under a license such as the License for Computer Programs (Article 14) contained in Motorola’s Terms and Conditions of Sale, Rev.
Page 6 Place holder...
Page 7: Table Of Contents
VMEbus BERR* ...1-49 Local DRAM Parity Error ...1-49 VMEchip2 ...1-49 Bus Error Processing ...1-49 Description of Error Conditions on the MVME172 ...1-50 MPU Parity Error...1-50 MPU Off-board Error ...1-51 MPU TEA - Cause Unidentified ...1-51 MPU Local Bus Time-out ...1-51 DMAC VMEbus Error ...1-52...
Page 8 SCSI Off-Board Error ... 1-56 SCSI LTO Error ... 1-56 Example of the Proper Use of Bus Timers ... 1-57 MVME172 MC68060 Indivisible Cycles ... 1-58 Illegal Access to IP Modules from External VMEbus Masters ... 1-59 CHAPTER 2 VMEchip2 Introduction ...
Page 9 VMEbus Slave Address Translation Select Register 1 ...2-30 VMEbus Slave Address Translation Address Offset Register 2 ...2-31 VMEbus Slave Address Translation Select Register 2 ...2-31 VMEbus Slave Write Post and Snoop Control Register 2 ...2-32 VMEbus Slave Address Modifier Select Register 2 ...2-33 VMEbus Slave Write Post and Snoop Control Register 1 ...2-35 VMEbus Slave Address Modifier Select Register 1 ...2-36 Programming the Local Bus to VMEbus Map Decoders ...2-37...
Page 10 MPU Status and DMA Interrupt Count Register ... 2-63 DMAC Status Register ... 2-64 Programming the Tick and Watchdog Timers... 2-65 VMEbus Arbiter Time-out Control Register ... 2-65 DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register ... 2-66 VME Access, Local Bus, and Watchdog Time-out Control Register ... 2-67 Prescaler Control Register ...
Page 11 Interrupt Level Register 4 (bits 24-31) ...2-94 Interrupt Level Register 4 (bits 16-23) ...2-95 Interrupt Level Register 4 (bits 8-15) ...2-95 Interrupt Level Register 4 (bits 0-7) ...2-96 Vector Base Register ...2-96 I/O Control Register 1 ...2-97 I/O Control Register 2 ...2-98 I/O Control Register 3 ...2-98 Miscellaneous Control Register ...2-99 GCSR Programming Model...2-101...
Page 12 LANC Bus Error Interrupt Control Register ... 3-32 SCSI Error Status Register ... 3-33 General Purpose Inputs Register ... 3-33 MVME172 Version Register ... 3-35 SCSI Interrupt Control Register ... 3-36 Tick Timer 3 and 4 Compare and Counter Registers ... 3-37 Bus Clock Register ...
Page 13 CHAPTER 4 IP2 Chip Introduction...4-1 Summary of Major Features ...4-1 Functional Description...4-2 General Description ...4-2 Cache Coherency ...4-2 Local Bus to IndustryPack DMA Controllers...4-3 Clocking Environments and Performance ...4-5 Programmable Clock ...4-7 Error Reporting ...4-7 Error Reporting as a Local Bus Slave ...4-7 Error Reporting as a Local Bus Master ...4-7 IndustryPack Error Reporting...4-8 Interrupts...4-8...
Page 14 IP to Local Bus Data Routing... 4-52 Memory Space Accesses ... 4-52 I/O and ID Space Accesses ... 4-54 CHAPTER 5 MCECC Introduction ... 5-1 Features... 5-1 Functional Description ... 5-2 General Description... 5-2 Performance... 5-2 Cache Coherency... 5-3 ECC ... 5-4 Cycle Types...
Page 15 Defaults Register 2...5-36 Initialization ...5-37 Syndrome Decode ...5-39 APPENDIX A Related Documentation Motorola Computer Group Documents ...A-1 Literature Updates...A-2 Manufacturers’ Documents...A-2 APPENDIX B Using Interrupts on the MVME172 Introduction... B-1 VMEchip2 Tick Timer 1 Periodic Interrupt Example ... B-1 INDEX...
Page 16 Table 1-3. 200/300-Series MVME172 Local Bus Memory Map ... 1-10 Table 1-4. 400/500-Series MVME172 Local Bus Memory Map ... 1-12 Table 1-5. 200/300-Series MVME172 Local I/O Devices Memory Map ... 1-14 Table 1-6. 400/500-Series MVME172 Local I/O Devices Memory Map ... 1-18 Table 1-7.
Page 17 Table 5-1. MCECC Specifications...5-3 Table 5-2. MCECC Internal Register Memory Map, Part 1 ...5-10 Table 5-3. MCECC Internal Register Memory Map, Part 2 ...5-12 Table A-1. Motorola Computer Group Documents ...A-1 Table A-2. Manufacturers’ Documents ...A-2 xvii...
Page 18 xviii...
Page 19: Introduction
All programmable registers in the MVME172 that reside in ASICs are covered in the chapters on those ASICs. Chapter 2 covers the VMEchip2, Chapter 3 covers the MC2 chip, and Chapter 4 covers the IP2 chip. Chapter 5 covers the MCECC chip, used only on 200/300-Series MVME172.
Page 20 I/O devices. The MVME712 series transition boards were designed to support the MVME167 boards, but can be used on the MVME172 by following some special precautions. (Refer to the section on the Serial Communications Interface in the MVME172 installation and use manual furnished with your 400/500-Series MVME172, for more information.)
Page 21: Table 1-1. Mvme172 Features Summary
Two 32-bit Tick Timers and Watchdog Timer in the VMEchip2 ASIC) for periodic interrupts Software Eight software interrupts (for MVME172 versions that have the VMEchip2) Interrupts Four serial ports, both EIA-232-D RJ- Serial port controller Optional Small Computer Systems Interface (SCSI) bus interface with 32-bit...
Page 22: Requirements
Board Description and Memory Maps Table 1-1. MVME172 Features Summary Feature interfaces with DMA VMEbus VMEbus system controller functions interface VMEbus interface to local bus (A24/A32, (boards may be D8/D16/D32 (D8/D16/D32/D64 BLT) (BLT = Block Transfer) special ordered without the...
Page 23: Block Diagrams
Flash memory with debugger code). To use the 172Bug package, MVME172Bug, in such models, be sure that the General Purpose Readable Jumpers Header is configured for the EPROM memory map. Refer to Chapters 3 and 4 of your MVME172 installation and use manual for further details. http://www.mcg.mot.com/literature...
Page 24: Figure 1-1. 200/300-Series Mvme172 Block Diagram
Board Description and Memory Maps Figure 1-1. 200/300-Series MVME172 Block Diagram Computer Group Literature Center Web Site...
Page 25: Figure 1-2. 400/500-Series Mvme172 Block Diagram
Functional Description Figure 1-2. 400/500-Series MVME172 Block Diagram http://www.mcg.mot.com/literature...
Page 26: Table 1-2. Redundant Functions In The Vmechip2 And Mc2 Chip
Implemented also in the ABORT VMEchip2, but with a different bit organization (refer to the VMEchip2 description in Chapter 2). In the MVME172, the switch is wired to the MC2 chip, not the VMEchip2. ABORT 7. The SRAM and PROM decoder in the VMEchip2 (version 2) must be disabled by software before any accesses are made to these address spaces.
Page 27: Vmebus Interface And Vmechip2
The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the MVME172, Transfer Types 0, 1, and 2 define the normal address range. Table 1-2 is the entire http://www.mcg.mot.com/literature...
Page 28: Table 1-3. 200/300-Series Mvme172 Local Bus Memory Map
I/O space must be marked cache inhibit and serialized in its page table. Table 1-3 on page 1-10 for the 200/300-Series MVME172, and defines the map for the local I/O devices for the 400/500-Series MVME172. Table 1-3. 200/300-Series MVME172 Local Bus Memory Map Address Range Programmable Programmable Programmable...
Page 29 EPROM size and by control bit V11 in the MC2 chip ASIC. Refer to the EPROM/Flash configuration tables in your MVME172 installation manual for further details. 2. This area is user-programmable. The DRAM and SRAM decoder is programmed in the MC2 chip, the local-to- VMEbus decoders are programmed in the VMEchip2, and the IP memory space is programmed in the IP2.
Page 30: Table 1-4. 400/500-Series Mvme172 Local Bus Memory Map
Board Description and Memory Maps Table 1-4. 400/500-Series MVME172 Local Bus Memory Map Address Range Programmable Programmable Programmable Programmable Programmable Programmable Programmable $FF800000 - $FF9FFFFF $FFA00000 - $FFBFFFFF $FFC00000 - $FFCFFFFF $FFD00000 - $FFDFFFFF $FFE00000 - $FFE7FFFF $FFE80000 - $FFEFFFFF...
Page 31 Memory Maps Register at address $FFF42048, bit 24. PROM/Flash is disabled at the low address space with PROM Control Register at address $FFF42040, bit 20. 2. This area is user-programmable. The DRAM and SRAM decoder is programmed in the MC2 chip, the local-to-VMEbus decoders are programmed in the VMEchip2, and the IP memory space is programmed in the IP2 chip.
Page 32: Table 1-5. 200/300-Series Mvme172 Local I/O Devices Memory Map
Board Description and Memory Maps Table 1-5 Devices" portion of the local bus main memory map for the 200/300-Series and 400/500-Series MVME172, respectively. Table 1-5. 200/300-Series MVME172 Local I/O Devices Memory Map Address Range $FFF00000 - $FFF3FFFF $FFF40000 - $FFF400FF...
Page 33: Table 1-6. 400/500-Series Mvme172 Local I/O Devices Memory Map
Table 1-5. 200/300-Series MVME172 Local I/O Devices Memory Map Address Range $FFF58280 - $FFF582FF IP2 IP_c ID $FFF58300 - $FFF5837F IP2 IP_d I/O $FFF58380 - $FFF583FF IP2 IP_d ID Read $FFF58400 - $FFF584FF IP2 IP_ab I/O $FFF58500 - $FFF585FF IP2 IP_cd I/O...
Page 34 Board Description and Memory Maps Table 1-5. 200/300-Series MVME172 Local I/O Devices Memory Map Address Range $FFFBC800 - $FFFBC81F $FFFBD000 - $FFFBFFFF $FFFC0000 - $FFFCFFFF $FFFD0000 - $FFFEFFFF 1-16 (Continued) Devices Accessed Reserved Reserved M48T58 (BBRAM, TOD Clock) Reserved Computer Group Literature Center Web Site...
Page 35 Memory Maps Notes 1. For a complete description of the register bits, refer to the data sheet for the specific chip. For a more detailed memory map, refer to the following detailed peripheral device memory maps. 2. The SCC is an 8-bit device located on an MC2 chip private data bus.
Page 36 Board Description and Memory Maps Table 1-6. 400/500-Series MVME172 Local I/O Devices Memory Map Address Range $FFF00000 - $FFF3FFFF $FFF40000 - $FFF400FF $FFF40100 - $FFF401FF $FFF40200 - $FFF40FFF $FFF41000 - $FFF41FFF $FFF42000 - $FFF42FFF $FFF43000 - $FFF44FFF $FFF45000 - $FFF45FFF...
Page 37 Table 1-6. 400/500-Series MVME172 Local I/O Devices Memory Map Address Range $FFF58980 - $FFF589FF Reserved $FFF58A00 - $FFF58A7F Reserved $FFF58A80 - $FFF58AFF Reserved $FFF58B00 - $FFF58B7F Reserved $FFF58B80 - $FFF58BFF Reserved $FFF58C00 - $FFF58CFF Reserved $FFF58D00 - $FFF58DFF Reserved $FFF58E00 - $FFF58EFF...
Page 38 Board Description and Memory Maps Notes 1. For a complete description of the register bits, refer to the 1-20 data sheet for the specific chip. For a more detailed memory map, refer to the following detailed peripheral device memory maps. 2.
Page 39: Detailed I/O Memory Maps
53C710 SCSI chip MK48T58 BBRAM/TOD clock BBRAM configuration area TOD clock Note Manufacturers’ errata sheets for the various chips are available by contacting your local Motorola sales representative. A non-disclosure agreement may be required. http://www.mcg.mot.com/literature Memory Maps Table 1-7 Table 1-8...
Page 40: Table 1-7. Vmechip2 Memory Map (Sheet 1 Of 3)
Board Description and Memory Maps Table 1-7. VMEchip2 Memory Map (Sheet 1 of 3) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: MAST MAST GCSR GROUP SELECT TICK TICK IRQ 1 1-22 SLAVE ENDING ADDRESS 1 SLAVE ENDING ADDRESS 2 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER MASTER ENDING ADDRESS 1...
Page 41 ADDER MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MASTER AM 2 MAST MAST ROBN FAIR DMA LB SNP MODE LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER DMA TABLE INTERRUPT COUNT STAT This sheet begins on facing page. http://www.mcg.mot.com/literature SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2...
Page 42 Board Description and Memory Maps Table 1-7. VMEchip2 Memory Map (Sheet 2 of 3) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: SCON FAIL FAIL FAIL AC FAIL IRQ LEVEL VME IACK IRQ LEVEL IRQ LEVEL SPARE IRQ LEVEL VECTOR BASE REGISTER 0 1-24 BGTO...
Page 43 LOCAL ACCESS TIMER TIMER COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW COUNTER 2 SCALER P ERROR IRQ LEVEL SIG 1 IRQ LEVEL IRQ LEVEL VME IRQ 4 IRQ LEVEL GPIOO This sheet begins on facing page. http://www.mcg.mot.com/literature PRESCALER TIME OUT CLOCK ADJUST SELECT OVERFLOW...
Page 44 Board Description and Memory Maps Table 1-7. VMEchip2 Memory Map (Sheet 3 of 3) VMEchip2 GCSR Base Address = $FFF40100 Offsets Local -bus 1-26 Bit Numbers Chip Revision General Purpose Control and Status Register 0 General Purpose Control and Status Register 1 General Purpose Control and Status Register 2 General Purpose Control and Status Register 3 General Purpose Control and Status Register 4...
Page 45: Table 1-8. Mc2 Chip Register Map
DRAM/SRAM SRAM Space Options Size Reserved LANC Interrupt Control General Purpose MVME172 Version Inputs Tick Timer 3 Compare Register Tick Timer 3 Counter Register Tick Timer 4 Compare Register Tick Timer 4 Counter Register EPROM Access Flash Parameter Time Control...
Page 46: Table 1-9. Ip2 Chip Overall Memory Map
Board Description and Memory Maps The following memory map table includes all devices selected by the IP2 chip map decoder. Table 1-9. IP2 Chip Overall Memory Map Address Range Programmable Programmable Programmable Programmable $FFF58000-$FFF5807F $FFF58080-$FFF580BF $FFF580C0-$FFF580FF $FFF58100-$FFF5817F $FFF58180-$FFF581BF $FFF581C0-$FFF581FF $FFF58200-$FFF5827F $FFF58280-$FFF582BF $FFF582C0-$FFF582FF $FFF58300-$FFF5837F...
Page 47: Table 1-10. Ip2 Chip Memory Map - Control And Status Registers
Table 1-10. IP2 Chip Memory Map - Control and Status Registers IP2 Chip Base Address = $FFFBC000 Register Register Offset Name CHIP ID CHIP REVISION RESERVED VECTOR BASE IP_a MEM a_BASE31 a_BASE30 BASE UPPER IP_a MEM a_BASE23 a_BASE22 BASE LOWER IP_b MEM b_BASE31 b_BASE30...
Page 48 Board Description and Memory Maps Table 1-10. IP2 Chip Memory Map - Control and Status Registers Register Register Offset Name IP_a a_ERR GENERAL CONTROL IP_b b_ERR GENERAL CONTROL IP_c c_ERR GENERAL CONTROL IP_d d_ERR GENERAL CONTROL RESERVED IP CLOCK ARBITRATION CONTROL IP RESET 1-30...
Page 49 Table 1-10. IP2 Chip Memory Map - Control and Status Registers Register Register Offset Name DMAC for IndustryPack a, request 0. This register set is referred to as DMACa in the text. DMA_a DLBE STATUS DMA_a INT CTRL DMA ENABLE RESERVED DMA_a CON- DHALT...
Page 50 Board Description and Memory Maps Table 1-10. IP2 Chip Memory Map - Control and Status Registers Register Register Offset Name DMAC for IndustryPack b, request 0 or for IndustryPack a, request 1. This register set is referred to as DMACb in the text. DMA_b STATUS DMA_b INT...
Page 51 Table 1-10. IP2 Chip Memory Map - Control and Status Registers Register Register Offset Name DMAC for IndustryPack c, request 0. This register set is referred to as DMACc in the text. DMA_c DLBE STATUS DMA_c INT CTRL DMA ENABLE RESERVED DMA_c CON- DHALT...
Page 52 Board Description and Memory Maps Table 1-10. IP2 Chip Memory Map - Control and Status Registers Register Register Offset Name DMAC for IndustryPack d, request 0 or for IndustryPack c, request 1, and for PACER CLOCK. This register set, not including the Pacer DMA_d STATUS DMA_d INT...
Page 53: Table 1-11. Mcecc Internal Register Memory Map
CONTROL PACER GEN PLTY CONTROL PACER TIMER PACER TIMER The following MCECC memory map applies only to the 200/300-Series MVME172 boards. Table 1-11. MCECC Internal Register Memory Map MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Offset Name...
Page 54 Board Description and Memory Maps Table 1-11. MCECC Internal Register Memory Map (Continued) MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Offset Name SCRUB PRESCALE SCRUB TIMER SCRUB TIMER SCRUB ADDR CNTRL SCRUB ADDR CNTRL SCRUB ADDR CNTRL SCRUB ADDR CNTRL ERROR LOGGER ERROR ADDRESS...
Page 55: Table 1-12. Z85230 Scc Register Addresses
Table 1-12. Z85230 SCC Register Addresses Z85230 SCC Register SCC #1 (All MVME172 modules) SCC #2 (200/300-Series MVME172 only) Note A bug in MVME172s that have MC2 chip revision $01 does not allow the data registers to be accessed directly. You must access them indirectly via the SCC chip.
Page 56: Table 1-13. 82596Ca Ethernet Lan Memory Map
Board Description and Memory Maps Address $FFF46000 $FFF46004 Notes 1. Refer to the MPU Port and MPU Channel Attention 1-38 Table 1-13. 82596CA Ethernet LAN Memory Map 82596CA Ethernet LAN Directly Accessible Registers Data Bits Upper Command Word MPU Channel Attention (CA) registers in Chapter 3.
Page 57: Table 1-14. 53C710 Scsi Memory Map
Table 1-14. 53C710 SCSI Memory Map Base Address is $FFF47000 Big Endian Mode SIEN SOCL SBCL SSTAT2 CTEST3 CTEST7 LCRC DCMD DCNTL Note Accesses may be 8-bit or 32-bit, but not 16-bit. http://www.mcg.mot.com/literature 53C710 Register Address Map SDID SCNTL1 SCNTL0 SODL SXFER SCID...
Page 58: Bbram/Tod Clock Memory Map
The first area is reserved for user data. The second area is used by Motorola networking software. The third area may be used by an operating system. The fourth area is used by the MVME172 board debugger (MVME172Bug). The fifth area, detailed in the configuration area.
Page 59: Table 1-16. Bbram Configuration Area Memory Map
1Board Description and Memory Maps 0Memory Maps Table 1-16. BBRAM Configuration Area Memory Map Address Range $FFFC1EF8 - $FFFC1EFB $FFFC1EFC - $FFFC1F07 $FFFC1F08 - $FFFC1F17 $FFFC1F18 - $FFFC1F27 $FFFC1F28 - $FFFC1F2B $FFFC1F2C - $FFFC1F31 $FFFC1F32 - $FFFC1F33 $FFFC1F34 - $FFFC1F35 $FFFC1F36 - $FFFC1F3D $FFFC1F3E - $FFFC1F45 $FFFC1F46 - $FFFC1F4D...
Page 60: Table 1-17. Tod Clock Memory Map
1-42 Description IP_d Board Serial Number IP_d Board PWB Reserved Checksum IP_c and IP_d are not used on 200/300-Series MVME172 modules. Table 1-17. TOD Clock Memory Map Data Bits D7 D6 D5 D4 D3 D2 D1 D0 Calibration R = Read Bit...
Page 61 The data structure of the configuration bytes starts at $FFFC1EF8 and is as follows. struct brdi_cnfg { The fields are defined as follows: 1. Four bytes are reserved for the revision or version of this structure. This revision is stored in ASCII format, with the first two bytes being the major version numbers and the last two bytes being the http://www.mcg.mot.com/literature char...
Page 62 01-W is required for a set. Additional boards in a set are defined by a structure for that set. For example, for an MVME172 board with MC68060, SCSI, Ethernet, 4MB DRAM, and 512KB SRAM, at revision A, the PWA field contains: 01-W318 x B01A (The 12 characters are followed by four blanks.)
Page 63 9. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the memory mezzanine board in ASCII format. This does not include the mezzanine at revision A, the PWB field contains: 10. Eight bytes are reserved for the serial number assigned to the memory mezzanine board in ASCII format.
Page 64: Interrupt Acknowledge Map
IndustryPack d. even 256 bytes. in the Debugging Package for Motorola 68K CISC CPUs User’s Manual) for security and data integrity of the configuration area of the NVRAM. This data is stored in hexadecimal format.
Page 65: Vmebus Accesses To The Local Bus
GCSR in the VMEbus short I/O space. Software Support Considerations The MVME172 is a complex board that interfaces to the VMEbus and SCSI bus. These multiple bus interfaces raise the issue of cache coherency and support of indivisible cycles. There are also many sources of bus error.
Page 66: Cache Coherency
DRAM parity error occurs and parity checking is enabled, or a VME bus error occurs during a VMEbus access. Note The devices on the MVME172 that are able to assert a local bus error are described below. Local Bus Time-out...
Page 67: Vmebus Access Time-Out
(such as parity error). Local DRAM Parity Error Note The 400/500-Series MVME172 models do not contain parity DRAM. When parity checking is enabled, the current bus master receives a bus error if it is accessing the local DRAM and a parity error occurs.
Page 68: Description Of Error Conditions On The Mvme172
Description of Error Conditions on the MVME172 This section list the various error conditions that are reported by the MVME172 hardware. A subsection heading identifies each type of error condition. A standard format gives a description of the error, indicates how...
Page 69: Mpu Off-Board Error
Comments: This can be caused by a VMEbus time-out, a VMEbus BERR, or an MVME172 VMEbus access time-out. The latter is the time from when the VMEbus has been requested to when it is granted. MPU TEA - Cause Unidentified Description: An error occurred while the MPU was attempting an access.
Page 70: Dmac Vmebus Error
Parity error while the DMAC was reading DRAM. MPU Notification: DMAC interrupt (when enabled). Status: The DLPE bit is set in the DMAC Status Register (address $FFF40048 bit 1-52 The 400/500-Series MVME172 models do not contain parity DRAM. Computer Group Literature Center Web Site...
Page 71: Dmac Off-Board Error
Comments: If the TBL bit is set (address $FFF40048 bit 2) the error occurred during a command table access, otherwise the error occurred during a data access. DMAC Off-board Error Description: Error encountered while the local bus side of the DMAC was attempting to go to the VMEbus.
Page 72: Dmac Tea - Cause Unidentified
Parity error while the LANCE was reading DRAM MPU. Notification: MC2 chip Interrupt (LAN ERROR IRQ). Status: MC2 chip LAN Error Status Register ($FFF42028). 1-54 The 400/500-Series MVME172 models do not contain parity DRAM. Computer Group Literature Center Web Site...
Page 73: Lan Off-Board Error
Comments: The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the MC2 chip. Control for the interrupt is in the MC2 chip LAN Error Interrupt Control Register ($FFF4202B). LAN Off-Board Error Description: Error encountered while the LANCE was attempting to go to the VMEbus.
Page 74: Scsi Parity Error
53C710 interrupt enables are controlled in the 53C710 and in the MC2 chip SCSI Interrupt Control Register ($FFF4202F). SCSI LTO Error Description: Local Bus Time-out occurred while the 53C710 was local bus master. 1-56 The 400/500-Series MVME172 models do not contain parity DRAM. Computer Group Literature Center Web Site...
Page 75: Example Of The Proper Use Of Bus Timers
Therefore, it is recommended this timer be set to a small value, such as 256 sec. The next timer to take over when one MVME172 accesses another is the VMEbus access timer. This measures the time between when the VMEbus has been address decoded and hence a VMEbus request has been made, http://www.mcg.mot.com/literature...
Page 76: Mvme172 Mc68060 Indivisible Cycles
Before an MVME172 access to another MVME172 can complete, however, the VMEchip2 on the accessed MVME172 must decode a slave access and request the local bus of the second MVME172. When the local bus is granted (any in-process onboard transfers have completed) then the local bus timer of the accessed MVME172 starts.
Page 77: Illegal Access To Ip Modules From External Vmebus Masters
VMEbus cycles, and they are not guaranteed indivisible. Illegal Access to IP Modules from External VMEbus Masters When a device other than the local MVME172 is operating as VMEbus master, access by that device to the local IP modules is subject to restrictions.
Page 78 Board Description and Memory Maps 1-60 Computer Group Literature Center Web Site...
Page 79: Introduction
Introduction This chapter describes the VMEchip2 ASIC, local bus to VMEbus interface chip. The VMEchip2 interfaces the local bus to the VMEbus. In addition to the VMEbus defined functions, the VMEchip2 includes a local bus to VMEbus DMA controller, VME board support features, and Global Control and Status Registers (GCSR) for interprocessor communications.
Page 80 VMEchip2 VMEbus Bus to Local Bus Interface: – Programmable VMEbus map decoder. – Programmable AM decoder. – Programmable local bus snoop enable. – Simple VMEbus to local bus address translation. – 8-bit, 16-bit and 32-bit VMEbus data width. – 8-bit, 16-bit and 32-bit block transfer. –...
Page 81 VMEbus Interrupter: – Software-configured IRQ1-IRQ7 interrupt request level. – 8-bit software-programmed status/ID register. VMEbus System Controller: – Arbiter with software-configured arbitration modes: Priority (PRI), Round-Robin-Select (RRS), and Single-level (SGL). – Programmable arbitration timer. – IACK daisy-chain driver. – Programmable bus timer. –...
Page 82: Functional Blocks
VMEchip2 Functional Blocks The following sections provide an overview of the functions provided by the VMEchip2. See Figure 2-1 for a block diagram of the VMEchip2. A detailed programming model for the local control and status registers (LCSR) is provided in the following section. A detailed programming model for the global control and status registers (GCSR) is provided in the next section.
Page 83: Figure 2-1. Vmechip2 Block Diagram
Functional Blocks Figure 2-1. VMEchip2 Block Diagram http://www.mcg.mot.com/literature...
Page 84 VMEchip2 Using the four programmable map decoders, separate VMEbus maps can be created, each with its own attributes. For example, one map can be configured as A32, D32 with write posting enabled while a second map can be A24, D16 with write posting disabled. The first I/O map decoder decodes local bus addresses $FFFF0000 through $FFFFFFFF as the short I/O A16/D16 or A16/D32 area, and the other provides an A24/D16 space at $F0000000 to $F0FFFFFF and an A32/D16...
Page 85: Local Bus To Vmebus Requester
have been accessed. This enhances the portability of software because it allows software to run on the system regardless of the physical organization of global memory. Using the local bus map decoder attribute register, the AM code that the master places on the VMEbus can be programmed under software control. The VMEchip2 includes a software-controlled VMEbus access timer, and it starts ticking when the chip is requested to do a VMEbus data transfer or an interrupt acknowledge cycle.
Page 86 VMEchip2 The requester requests the bus if any of the following conditions occur: 1. The local bus master initiates either a data transfer cycle or an 2. The chip is requested to acquire control of the VMEbus as signaled 3. The chip is requested to acquire control of the VMEbus as signaled The local bus to VMEbus requester in the VMEchip2 implements a fair mode.
Page 87: Vmebus To Local Bus Interface
VMEbus to Local Bus Interface The VMEbus to local bus interface allows an off-board VMEbus master access to onboard resources. The VMEbus to local bus interface includes the VMEbus slave, write post buffer, and local bus master. Adhering to the IEEE 1014-87 VMEbus Standard, the slave can withstand address-only cycles, as well as address pipelining, and respond to unaligned transfers.
Page 88: Local Bus To Vmebus Dma Controller
VMEchip2 Each map decoder includes an alternate address register and an alternate address select register. These registers allow any or all of the upper 16 VMEbus address lines to be replaced by signals from the alternate address register. This allows the address of local resources to be different from their VMEbus address.
Page 89 Using control register bits in the LCSR, the DMAC can be configured to provide the following VMEbus capabilities: Addressing capabilities: Data transfer capabilities: Using the DMA AM control register, the address modifier code that the VMEbus DMA controller places on the VMEbus can be programmed under software control.
Page 90: No Address Increment Dma Transfers
VMEbus address. The DMA controller also allows DMA transfers without incrementing the local bus address, however the MVME172 does not have any onboard devices that benefit from not incrementing the local bus address. The transfer mode on the VMEbus may be D16, D16/BLT, D32, D32/BLT or D64/BLT.
Page 91: Dmac Vmebus Requester
transfers which are not an even byte count or start at an odd address, with respect to the port size. A 16-bit device should respond with VA<1> high or low. Devices on the local bus should respond to any combination of LA<3..2>.
Page 92: Tick And Watchdog Timers
VMEchip2 The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer. The requester implements a fair mode. By setting the DFAIR bit, the requester refrains from requesting the bus until it detects its assigned request line in its negated state.
Page 93: Tick Timers
Tick Timers The VMEchip2 includes two general purpose tick timers. These timers can be used to generate interrupts at various rates or the counters can be read at various times for interval timing. The timers have a resolution of 1 s and when free running, they roll over every 71.6 minutes.
Page 94: Vmebus Interrupter
VMEchip2 VMEbus Interrupter The interrupter provides all the signals necessary to allow software to request interrupt service from a VMEbus interrupt handler. The chip connects to all signals that a VMEbus interrupter is required to drive and monitor. Requiring no external jumpers, the chip provides the means for software to program the interrupter to request an interrupt on any one of the seven interrupt request lines.
Page 95: Vmebus System Controller
VMEbus System Controller With the exception of the optional SERCLK Driver and the Power Monitor, the chip includes all the functions that a VMEbus System Controller must provide. The System Controller is enabled/disabled with the aid of an external jumper (the only jumper required in a VMEchip2 based VMEbus interface).
Page 96: Reset Driver
VMEchip2 In addition to the VMEbus timer, the chip contains a local bus timer. This timer asserts the local TEA when the local bus cycle maintained in its asserted state for longer that the programmed time-out period. This timer can be enabled or disabled under software control. The time-out period can be programmed for 8, 64, or 256 secs.
Page 97 Functional Blocks The write post bus error interrupter is an edge-sensitive interrupter connected to the local bus to VMEbus write post bus error signal line. The VMEbus IRQ1 edge-sensitive interrupter is an edge-sensitive interrupter connected to the VMEbus IRQ1 signal line. This interrupter is used when one of the tick timers is connected to the IRQ1 signal line.
Page 98: Global Control And Status Registers
VMEchip2 and monitor. On the local bus, the interrupt handler is designed to comply with the interrupt handling signaling protocol of the MC68060 microprocessor. Global Control and Status Registers The VMEchip2 includes a set of registers that are accessible from both the VMEbus and the local bus.
Page 99 Line 4 defines the operations possible on the register bits as follows: W/AC This bit can be set and it is automatically cleared. This bit can Line 5 defines the state of the bit following a reset as follows: A summary of the LCSR is shown in Table 2-1. http://www.mcg.mot.com/literature This bit is a read-only status bit.
Page 100: Table 2-1. Vmechip2 Memory Map - Lcsr Summary (Sheet 1 Of 2)
VMEchip2 Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: MAST MAST GCSR GROUP SELECT TICK TICK IRQ 1 2-22 SLAVE ENDING ADDRESS 1 SLAVE ENDING ADDRESS 2 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER MASTER ENDING ADDRESS 1...
Page 101 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MASTER AM 2 MAST MAST ROBN FAIR DMA LB SNP MODE LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER DMA TABLE INTERRUPT COUNT STAT...
Page 102 VMEchip2 Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 2 of 2) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: SCON FAIL FAIL FAIL AC FAIL IRQ LEVEL VME IACK IRQ LEVEL IRQ LEVEL SPARE IRQ LEVEL VECTOR BASE REGISTER 0 2-24 BGTO TIME OFF...
Page 103 LOCAL ACCESS TIMER TIMER COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW COUNTER 2 SCALER P ERROR IRQ LEVEL SIG 1 IRQ LEVEL IRQ LEVEL VME IRQ 4 IRQ LEVEL GPIOO This sheet begins on facing page. http://www.mcg.mot.com/literature PRESCALER TIME OUT CLOCK ADJUST SELECT OVERFLOW...
Page 104: Programming The Vmebus Slave Map Decoders
VMEchip2 Programming the VMEbus Slave Map Decoders This section includes programming information for the VMEbus to local bus map decoders. The VMEbus to local bus interface allows off-board VMEbus masters access to local onboard resources. The address of the local resources as viewed from the VMEbus is controlled by the VMEbus slave map decoders, which are part of the VMEbus to local bus interface.
Page 105 LCSR Programming Model A VMEbus slave map decoder is programmed by loading the starting address of the segment into the starting address register and the ending address of the segment into the ending address register. If the VMEbus address modifier codes indicate an A24 VMEbus address cycle, then the upper eight bits of the VMEbus address are forced to zero before the compare.
Page 106: Vmebus Slave Ending Address Register 1
VMEchip2 $FFF40010. The adders allow any size board to be mapped on any 64KB boundary. The adders are disabled and the address replacement method is used following reset. Write posting is enabled for the segment by setting the write post enable bit in the attribute register.
Page 107: Vmebus Slave Ending Address Register 2
VMEbus Slave Ending Address Register 2 ADR/SIZ NAME OPER RESET This register is the ending address register for the second VMEbus to local bus map decoder. VMEbus Slave Starting Address Register 2 ADR/SIZ NAME OPER RESET This register is the starting address register for the second VMEbus to local bus map decoder.
Page 108: Vmebus Slave Address Translation Select Register 1
VMEchip2 VMEbus Slave Address Translation Select Register 1 ADR/SIZ NAME OPER RESET This register is the address translation select register for the first VMEbus to local bus map decoder. The address translation select register value is based on the segment size (the difference between the VMEbus starting and ending addresses).
Page 109 VMEbus Slave Address Translation Address Offset Register 2 ADR/SIZ NAME OPER RESET This register is the address translation address register for the second VMEbus to local bus map decoder. It should be programmed to the local bus starting address. When the adder is enabled, this register is the offset value.
Page 110: Vmebus Slave Write Post And Snoop Control Register 2
VMEchip2 VMEbus Slave Write Post and Snoop Control Register 2 ADR/SIZ NAME OPER RESET This register is the slave write post and snoop control register for the second VMEbus to local bus map decoder. SNP2 ADDER2 2-32 $FFF40010 (8 bits [4 used] of 32) ADDER2 0 PS When this bit is high, write posting is enabled for the...
Page 111: Vmebus Slave Address Modifier Select Register 2
VMEbus Slave Address Modifier Select Register 2 ADR/SIZ NAME OPER RESET 0 PSL 0 PSL This register is the address modifier select register for the second VMEbus to local bus map decoder. There are three groups of address modifier select bits: DAT, PGM, BLK and D64;...
Page 112 VMEchip2 2-34 When this bit is high, the second map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, the second map decoder does not respond to VMEbus A32 access cycles. When this bit is high, the second map decoder responds to VMEbus user (non-privileged) access cycles.
Page 113: Vmebus Slave Write Post And Snoop Control Register 1
VMEbus Slave Write Post and Snoop Control Register 1 ADR/SIZ NAME OPER RESET This register is the slave write post and snoop control register for the first VMEbus to local bus map decoder. SNP1 ADDER1 http://www.mcg.mot.com/literature $FFF40010 (8 bits [4 used] of 32) ADDER1 0 PS When this bit is high, write posting is enabled for the...
Page 114: Vmebus Slave Address Modifier Select Register 1
VMEchip2 VMEbus Slave Address Modifier Select Register 1 ADR/SIZ NAME OPER RESET 0 PSL This register is the address modifier select register for the first VMEbus to local bus map decoder. There are three groups of address modifier select bits: DAT, PGM, BLK and D64; A24 and A32; and USR and SUP. At least one bit must be set from each group to enable the first map decoder.
Page 115: Programming The Local Bus To Vmebus Map Decoders
Programming the Local Bus to VMEbus Map Decoders This section includes programming information on the local bus to VMEbus map decoders and the GCSR base address registers. The local bus to VMEbus interface allows onboard local bus masters access to off-board VMEbus resources. The address of the VMEbus resources as viewed from the local bus is controlled by the local bus slave map decoders, which are part of the local bus to VMEbus interface.
Page 116 VMEchip2 Each of the four programmable local bus map decoders has a starting address, an ending address, an address modifier register with attribute bits, and an enable bit. The fourth decoder also has address translation registers. The addresses and bit definitions for these registers are in the tables below.
Page 117: Local Bus Slave (Vmebus Master) Ending Address Register 1
Write posting is enabled for the segment by setting the write post enable bit in the address modifier register. D16 transfers are forced by setting the D16 bit in the address modifier register. A segment is enabled by setting the enable bit. Segments should not be programmed to overlap. The first I/O map decoder maps the local bus address range $FFFF0000 to $FFFFFFFF to the A16 (short I/O) map of the VMEbus.
Page 118: Local Bus Slave (Vmebus Master) Starting Address Register 1
VMEchip2 Local Bus Slave (VMEbus Master) Starting Address Register 1 ADR/SIZ NAME OPER RESET This register is the starting address register for the first local bus to VMEbus map decoder. Local Bus Slave (VMEbus Master) Ending Address Register 2 ADR/SIZ NAME OPER RESET...
Page 119: Local Bus Slave (Vmebus Master) Ending Address Register 3
Local Bus Slave (VMEbus Master) Ending Address Register 3 ADR/SIZ NAME OPER RESET This register is the ending address register for the third local bus to VMEbus map decoder. Local Bus Slave (VMEbus Master) Starting Address Register 3 ADR/SIZ NAME OPER RESET This register is the starting address register for the third local bus to...
Page 120: Local Bus Slave (Vmebus Master) Address Translation Address Register 4
VMEchip2 Local Bus Slave (VMEbus Master) Starting Address Register 4 ADR/SIZ NAME OPER RESET This register is the starting address register for the fourth local bus to VMEbus map decoder. Local Bus Slave (VMEbus Master) Address Translation Address Register 4 ADR/SIZ NAME OPER...
Page 121: Local Bus Slave (Vmebus Master) Attribute Register 4
Local Bus Slave (VMEbus Master) Attribute Register 4 ADR/SIZ NAME OPER RESET 0 PS 0 PS This register is the attribute register for the fourth local bus to VMEbus bus map decoder. http://www.mcg.mot.com/literature $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes the VMEbus master uses for the segment defined by map decoder 4.
Page 122: Local Bus Slave (Vmebus Master) Attribute Register 3
VMEchip2 Local Bus Slave (VMEbus Master) Attribute Register 3 ADR/SIZ NAME OPER RESET 0 PS This register is the attribute register for the third local bus to VMEbus bus map decoder. 2-44 $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes the VMEbus master uses for the segment defined by map decoder 3.
Page 123: Local Bus Slave (Vmebus Master) Attribute Register 2
Local Bus Slave (VMEbus Master) Attribute Register 2 ADR/SIZ NAME OPER RESET 0 PS 0 PS This register is the attribute register for the second local bus to VMEbus bus map decoder. http://www.mcg.mot.com/literature $FFF40028 (8 bits of 32) O PS These bits define the VMEbus address modifier codes the VMEbus master uses for the segment defined by map decoder 2.
Page 124: Local Bus Slave (Vmebus Master) Attribute Register 1
VMEchip2 Local Bus Slave (VMEbus Master) Attribute Register 1 ADR/SIZ NAME OPER RESET 0 PS This register is the attribute register for the first local bus to VMEbus bus map decoder. 2-46 $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes the VMEbus master uses for the segment defined by map decoder 1.
Page 125: Vmebus Slave Gcsr Group Address Register
$FFF4002C (8 bits of 32) . . . GCSR Group Address Register 4 $00 PS These bits are compared with VMEbus address lines A8 through A15. The recommended group address for the MVME172 is $D2. LCSR Programming Model 2-47...
Page 126: Vmebus Slave Gcsr Board Address Register
VMEchip2 VMEbus Slave GCSR Board Address Register ADR/SIZ NAME OPER RESET This register defines the board address of the GCSR as viewed from the VMEbus. The GCSR address is defined by the group address and the board address. Once enabled, the GCSR register should not be reprogrammed unless the VMEchip2 is VMEbus master.
Page 127: Local Bus To Vmebus Enable Control Register
Local Bus to VMEbus Enable Control Register ADR/SIZ NAME OPER RESET This register is the map decoder enable register for the four programmable local bus to VMEbus map decoders. http://www.mcg.mot.com/literature $FFF4002C (4 bits of 32) 0 PSL When this bit is high, the first local bus to VMEbus map decoder is enabled.
Page 128: Local Bus To Vmebus I/O Control Register
VMEchip2 Local Bus to VMEbus I/O Control Register ADR/SIZ NAME I2EN OPER RESET 0 PSL This register controls the VMEbus short I/O map and the F page ($F0000000 through $FF7FFFFF) I/O map. I1SU I1WP I1D16 I1EN I2PD I2SU 2-50 $FFF4002C (8 bits of 32) I2WP I2SU I2PD...
Page 129: Rom Control Register
SIZE OPER RESET 0 PS This function is not used on the MVME172. http://www.mcg.mot.com/literature LCSR Programming Model When this bit is high, write posting is enabled to the local bus F page. When this bit is low, write posting is disabled to the local bus F page.
Page 130: Programming The Vmechip2 Dma Controller
VMEchip2 Programming the VMEchip2 DMA Controller This section includes programming information on the DMA controller, VMEbus interrupter, MPU status register, and local bus to VMEbus requester register. The VMEchip2 features a local bus -VMEbus DMA controller (DMAC). The DMAC has two modes of operation: command chaining, and direct. In the direct mode, the local bus address, the VMEbus address, the byte count, and the control register of the DMAC are programmed and the DMAC is enabled.
Page 131: Dmac Registers
Once the DMAC is enabled, the counter and control registers should not be modified by software. When the command chaining mode is used, the list of commands must be in local 32-bit memory and the entries must be four-byte aligned. A DMAC command list includes one or more DMAC command packets.
Page 132: Prom Decoder, Sram And Dma Control Register
This register controls the snoop control bits used by the DMAC when it is accessing table entries. SRAMS TBLSC ROM0 WAIT RMW This function is not used on the MVME172. 2-54 $FFF40030 (8 bits [6 used] of 32) WAIT RMW ROM0...
Page 133: Local Bus To Vmebus Requester Control Register
Local Bus to VMEbus Requester Control Register ADR/SIZ NAME ROBN OPER RESET 0 PS 0 PS This register controls the VMEbus request level, the request mode, and release mode for the local bus to VMEbus interface. LVREQL LVRWD LVFAIR http://www.mcg.mot.com/literature LCSR Programming Model $FFF40030 (8 bits [7 used] OF 32) LVFAIR...
Page 134: Dmac Control Register 1 (Bits 0-7)
VMEchip2 ROBN DMAC Control Register 1 (bits 0-7) ADR/SIZ NAME DHALT OPER RESET 0 PS This control register is loaded by the processor; it is not modified when the DMAC loads new values from the command packet. DREQL DRELM 2-56 When this bit is high, the VMEbus has been acquired in response to the DWB bit being set.
Page 135: Dmac Control Register 2 (Bits 8-15)
DFAIR DTBL DHALT DMAC Control Register 2 (bits 8-15) ADR/SIZ NAME INTE OPER RESET 0 PS This portion of the control register is loaded by the processor or by the DMAC when it loads the command word from the command packet. Because this register is loaded from the command packet in the command chaining mode, the descriptions here also apply to the control word in the command packet.
Page 136 VMEchip2 TVME LINC VINC INTE 2-58 This bit defines the direction in which the DMAC transfers data. When this bit is high, data is transferred to the VMEbus. When it is low, data is transferred to the local bus. When this bit is high, the local bus address counter is incremented during DMA transfers.
Page 137: Dmac Control Register 2 (Bits 0-7)
DMAC Control Register 2 (bits 0-7) ADR/SIZ NAME OPER RESET 0 PS This portion of the control register is loaded by the processor or the DMAC when it loads the command word from the command packet. Because this byte is loaded from the command packet in the command chaining mode, the descriptions here also apply to the control word in the command packet.
Page 138: Dmac Local Bus Address Counter
VMEchip2 DMAC Local Bus Address Counter ADR/SIZ NAME OPER RESET In the direct mode, this counter is programmed with the starting address of the data in local bus memory. DMAC VMEbus Address Counter ADR/SIZ NAME OPER RESET In the direct mode, this counter is programmed with the starting address of the data in VMEbus memory.
Page 139: Dmac Byte Counter
DMAC Byte Counter ADR/SIZ NAME OPER RESET In the direct mode, this counter is programmed with the number of bytes of data to be transferred. Table Address Counter ADR/SIZ NAME OPER RESET In the command chaining mode, this counter should be loaded by the processor with the starting address of the list of commands.
Page 140 VMEchip2 This register controls the VMEbus interrupter. IRQL IRQS IRQC IRQ1S 2-62 These bits define the level of the VMEbus interrupt generated by the VMEchip2. A VMEbus interrupt is generated by writing the desired level to these bits. These bits always read 0 and writing 0 to these bits has no effect. This bit is the IRQ status bit.
Page 141: Vmebus Interrupter Vector Register
DRAM data transfer. This bit is cleared by writing a one to the MCLR bit in this register. This bit is not defined for MVME172 implementation. When this bit is set, the MPU received a TEA and additional status was not provided.
Page 142: Dmac Status Register
VMEchip2 DMAIC DMAC Status Register ADR/SIZ NAME MLTO OPER RESET 0 PS This is the DMAC status register. DONE DLTO 2-64 The DMAC interrupt counter is incremented when an interrupt is sent to the local bus interrupter. The value in this counter indicates the number of commands processed when the DMAC is operated in the command chaining mode.
Page 143: Programming The Tick And Watchdog Timers
DRAM data transfer. This bit is cleared when the DMAC is enabled. This bit is not defined for MVME172 implementation. When this bit is set, the DMAC received a TEA and additional status was not provided. This bit is cleared when the DMAC is enabled.
Page 144: Dmac Ton/Toff Timers And Vmebus Global Time-Out Control Register
VMEchip2 DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register ADR/SIZ NAME OPER RESET This register controls the DMAC time off timer, the DMAC time on timer, and the VMEbus global time-out timer. VGTO TIME ON TIME OFF 2-66 $FFF4004C (8 bits of 32) TIME OFF TIME ON 0 PS...
Page 145: Vme Access, Local Bus, And Watchdog Time-Out Control Register
VME Access, Local Bus, and Watchdog Time-out Control Register ADR/SIZ NAME VATO OPER RESET 0 PS WDTO LBTO VATO http://www.mcg.mot.com/literature LCSR Programming Model $FFF4004C (8 bits of 32) LBTO 0 PS These bits define the watchdog time-out period: Bit Encoding Time-out 1 ms 2 ms...
Page 146: Prescaler Control Register
VMEchip2 Prescaler Control Register ADR/SIZ NAME OPER RESET The prescaler provides the various clocks required by the counters and timers in the VMEchip2. In order to specify absolute times from these counters and timers, the prescaler must be adjusted for different local bus clocks.
Page 147: Tick Timer 1 Compare Register
Tick Timer 1 Compare Register ADR/SIZ NAME OPER RESET The tick timer 1 counter is compared to this register. When they are equal, an interrupt is sent to the local bus interrupter and the overflow counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.
Page 148: Tick Timer 2 Compare Register
VMEchip2 Tick Timer 2 Compare Register ADR/SIZ NAME OPER RESET The tick timer 2 counter is compared to this register. When they are equal, an interrupt is sent to the local bus interrupter and the overflow counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.
Page 149: Board Control Register
Board Control Register ADR/SIZ NAME SCON OPER RESET RSWE BDFLO CPURS PURS BRFLI SFFL SCON http://www.mcg.mot.com/literature LCSR Programming Model $FFF40060 (8 bits [7 used] of 32) SFFL BRFLI PURS CPURS BDFLO RSWE 1 PSL switch enable bit is used with the “no RESET VMEbus interface”...
Page 150: Watchdog Timer Control Register
VMEchip2 Watchdog Timer Control Register ADR/SIZ NAME SRST OPER RESET 0 PS WDEN WDRSE WDS/L WDBFE WDTO WDCC 2-72 $FFF40060 (8 bits of 32) WDCS WDCC WDTO WDBFE WDS/L WDRSE WDEN 0 PSL When this bit is high, the watchdog timer is enabled. When this bit is low, the watchdog timer is not enabled.
Page 151: Tick Timer 2 Control Register
WDCS SRST Tick Timer 2 Control Register ADR/SIZ NAME OPER RESET COVF http://www.mcg.mot.com/literature When this bit is set high, the watchdog time-out status bit (WDTO bit in this register) is cleared. When this bit is set high, a SYSRESET signal is generated on the VMEbus.
Page 152: Tick Timer 1 Control Register
VMEchip2 Tick Timer 1 Control Register ADR/SIZ NAME OPER RESET COVF Prescaler Counter ADR/SIZ NAME OPER RESET The VMEchip2 has a 32-bit prescaler that provides the clocks required by the various timers in the chip. Access to the prescaler is provided for test purposes.
Page 153: Programming The Local Bus Interrupter
2VMEchip2 LCSR Programming Model Programming the Local Bus Interrupter The local bus interrupter is used by devices that wish to interrupt the local bus. There are 31 devices that can interrupt the local bus through the VMEchip2. In the general case, each interrupter has a level select register, an enable bit, a status bit, a clear bit, and for the software interrupts, a set bit.
Page 154: Table 2-3. Local Bus Interrupter Summary
VMEchip2 VMEbus IRQ1 VMEbus IRQ2 VMEbus IRQ3 VMEbus IRQ4 VMEbus IRQ5 VMEbus IRQ6 VMEbus IRQ7 Spare Software 0 Software 1 Software 2 Software 3 Software 4 Software 5 Software 6 Software 7 GCSR LM0 GCSR LM1 GCSR SIG0 GCSR SIG1 GCSR SIG2 GCSR SIG3 2-76...
Page 155 DMAC VMEbus Interrupter Acknowledge Tick Timer 1 Tick Timer 2 VMEbus IRQ1 Edge-Sensitive (Not used on MVME172) VMEbus Master Write Post Error VMEbus SYSFAIL (Not used on MVME172) VMEbus ACFAIL Notes 1. X = The contents of vector base register 0.
Page 156: Local Bus Interrupter Status Register (Bits 24-31)
0 PSL 0 PSL Tick timer 1 interrupt. Tick timer 2 interrupt VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME172. VMEbus master write post error interrupt. VMEbus SYSFAIL interrupt. Not used on MVME172. VMEbus ACFAIL interrupt. Computer Group Literature Center Web Site...
Page 157: Local Bus Interrupter Status Register (Bits 16-23)
Local Bus Interrupter Status Register (bits 16-23) ADR/SIZ NAME OPER RESET 0 PSL 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
Page 158: Local Bus Interrupter Status Register (Bits 8-15)
VMEchip2 Local Bus Interrupter Status Register (bits 8-15) ADR/SIZ NAME OPER RESET 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
Page 159: Local Bus Interrupter Status Register (Bits 0-7)
Local Bus Interrupter Status Register (bits 0-7) ADR/SIZ NAME SPARE VME7 OPER RESET 0 PSL 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
Page 160: Local Bus Interrupter Enable Register (Bits 24-31)
0 PSL Enable tick timer 1 interrupt. Enable tick timer 2 interrupt. Enable VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME172. Enable VMEbus master write post error interrupt. Enable VMEbus SYSFAIL interrupt. Not used on MVME172. Enable VMEbus ACFAIL interrupt.
Page 161: Local Bus Interrupter Enable Register (Bits 16-23)
Local Bus Interrupter Enable Register (bits 16-23) ADR/SIZ NAME EVIA EDMA OPER RESET 0 PSL 0 PSL This register is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
Page 162: Local Bus Interrupter Enable Register (Bits 8-15)
VMEchip2 Local Bus Interrupter Enable Register (bits 8-15) ADR/SIZ NAME ESW7 OPER RESET 0 PSL This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
Page 163: Local Bus Interrupter Enable Register (Bits 0-7)
Local Bus Interrupter Enable Register (bits 0-7) ADR/SIZ NAME SPARE EIRQ7 OPER RESET 0 PSL 0 PSL This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
Page 164: Software Interrupt Set Register (Bits 8-15)
VMEchip2 Software Interrupt Set Register (bits 8-15) ADR/SIZ NAME SSW7 OPER RESET 0 PSL This register is used to set the software interrupts. An interrupt is set by writing a one to it. The software interrupt set bits are: SSW0 SSW1 SSW2 SSW3...
Page 165: Interrupt Clear Register (Bits 16-23)
CSIG1 CSIG2 CSIG3 CDMA CVIA http://www.mcg.mot.com/literature Clear VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME172. Clear VMEbus master write post error interrupt. Clear VMEbus SYSFAIL interrupt. Not used on MVME172. Clear VMEbus ACFAIL interrupt. $FFF40074 (8 bits of 32) CSIG3...
Page 166: Interrupt Clear Register (Bits 8-15)
Clear software 5 interrupt. Clear software 6 interrupt. Clear software 7 interrupt. $FFF40078 (8 bits [6 used] of 32) ACF LEVEL 0 PSL Not used on MVME172. Computer Group Literature Center Web Site CSW2 CSW1 CSW0 AB LEVEL 0 PSL...
Page 167: Interrupt Level Register 1 (Bits 16-23)
$FFF40078 (8 bits [6 used] of 32) SYSF LEVEL 0 PSL error interrupt. $FFF40078 (8 bits [6 used] of 32) PE LEVEL 0 PSL edge-sensitive interrupt. Not used on MVME172. LCSR Programming Model WPE LEVEL 0 PSL IRQ1E LEVEL 0 PSL 2-89...
Page 168: Interrupt Level Register 1 (Bits 0-7)
VMEchip2 Interrupt Level Register 1 (bits 0-7) ADR/SIZ NAME OPER RESET This register is used to define the level of the tick timer 1 interrupt and the tick timer 2 interrupt. TICK1 LEVEL These bits define the level of the tick timer 1 interrupt. TICK2 LEVEL These bits define the level of the tick timer 2 interrupt.
Page 169: Interrupt Level Register 2 (Bits 16-23)
Interrupt Level Register 2 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the GCSR SIG2 interrupt and the GCSR SIG3 interrupt. SIG2 LEVEL These bits define the level of the GCSR SIG2 interrupt. SIG3 LEVEL These bits define the level of the GCSR SIG3 interrupt.
Page 170: Interrupt Level Register 2 (Bits 0-7)
VMEchip2 Interrupt Level Register 2 (bits 0-7) ADR/SIZ NAME OPER RESET This register is used to define the level of the GCSR LM0 interrupt and the GCSR LM1 interrupt. LM0 LEVEL These bits define the level of the GCSR LM0 interrupt. LM1 LEVEL These bits define the level of the GCSR LM1 interrupt.
Page 171: Interrupt Level Register 3 (Bits 16-23)
Interrupt Level Register 3 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the software 4 interrupt and the software 5 interrupt. SW4 LEVEL These bits define the level of the software 4 interrupt. SW5 LEVEL These bits define the level of the software 5 interrupt.
Page 172: Interrupt Level Register 3 (Bits 0-7)
The VMEbus level 7 (IRQ7) interrupt may be mapped to any local bus interrupt level. VIRQ7 LEVEL These bits define the level of the VMEbus IRQ7 interrupt. SPARE LEVELNot used on the MVME172. 2-94 $FFF40080 (8 bits [6 used] of 32)
Page 173: Interrupt Level Register 4 (Bits 16-23)
Interrupt Level Register 4 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the VMEbus IRQ5 interrupt and the VMEbus IRQ6 interrupt. The VMEbus level 5 (IRQ5) interrupt and the VMEbus level 6 (IRQ6) interrupt may be mapped to any local bus interrupt level.
Page 174: Interrupt Level Register 4 (Bits 0-7)
VMEchip2 Interrupt Level Register 4 (bits 0-7) ADR/SIZ NAME OPER RESET This register is used to define the level of the VMEbus IRQ1 interrupt and the VMEbus IRQ2 interrupt. The VMEbus level 1 (IRQ1) interrupt and the VMEbus level 2 (IRQ2) interrupt may be mapped to any local bus interrupt level.
Page 175: I/O Control Register 1
I/O Control Register 1 ADR/SIZ NAME MIEN SYSFL OPER RESET 0 PSL This register is a general purpose I/O control register. Bits 16-19 control the direction of the four General Purpose I/O pins (GPIO0-3). GPOEN0 GPOEN1 GPOEN2 GPOEN3 ABRTL ACFL SYSFL MIEN http://www.mcg.mot.com/literature...
Page 176: I/O Control Register 2
GPIOI3 I/O Control Register 3 ADR/SIZ NAME GPI7 OPER RESET This function is not used on the MVME172. 2-98 $FFF40088 (8 bits of 32) GPIOI3 GPIOI2 GPIOI1 GPIOI0 0 PS 0 PS 0 PS Connects to pin 16 of the Remote Status and Control Register.
Page 177: Miscellaneous Control Register
Miscellaneous Control Register ADR/SIZ NAME MPIRQEN REVEROM OPER RESET 0 PSL 0 PSL DISBGN ENINT DISBSYT http://www.mcg.mot.com/literature $FFF4008C (8 bits of 32) DISSRAM DISMST NOELBBSY DISBSYT 0 PSL 0 PS 0 PS When this bit is high, the VMEbus BGIN filters are disabled.
Page 178 VMEchip2 is driving local bus busy. When this bit is low, the on the MVME172 is lit when local bus reset is asserted, the VMEchip2 is driving local bus busy, or the VMEchip2 is driving the VMEbus address strobe.
Page 179: Gcsr Programming Model
GCSR Programming Model This section describes the programming model for the Global Control and Status Registers (GCSR) in the VMEchip2. The local bus map decoder for the GCSR registers is included in the VMEchip2. The local bus base address for the GCSR is $FFF40100. The registers in the GCSR are 16 bits wide and they are byte accessible from both the VMEbus and the local bus.
Page 180 VMEchip2 The location monitor status register provides the status of the location monitors. A location monitor bit is cleared when the VMEchip2 detects a VMEbus cycle to the corresponding location monitor address. When the LM0 or LM1 bits are cleared, an interrupt is set to the local bus interrupter. If the LM0 or LM1 interrupt is enabled in the local bus interrupter, then a local bus interrupt is generated.
Page 181: Programming The Gcsr
Programming the GCSR A complete description of the GCSR is provided in the following tables. Each register definition includes a table with five lines. Line 1 is the base address of the register as viewed from the local bus and as viewed from the VMEbus, and the number of bits defined in the table.
Page 182: Table 2-4. Vmechip2 Memory Map (Gcsr Summary)
VMEchip2 Table 2-4 shows a summary of the GCSR. Table 2-4. VMEchip2 Memory Map (GCSR Summary) VMEchip2 GCSR Base Address = $FFF40100 Offsets Local -bus LM3 LM2 LM1 LM0 SIG3 SIG2 SIG1 SIG0 RST 2-104 Bit Numbers Chip Revision General Purpose Control and Status Register 0 General Purpose Control and Status Register 1 General Purpose Control and Status Register 2 General Purpose Control and Status Register 3...
Page 183: Vmechip2 Revision Register
RESET This register is the VMEchip2 revision register. The revision level for the VMEchip2 starts at zero and is incremented if mask changes are required. The VMEchip2 used on the MVME172 is revision $01 or greater. VMEchip2 ID Register ADR/SIZ...
Page 184 VMEchip2 SIG0 SIG1 SIG2 SIG3 2-106 The SIG0 bit is set when a VMEbus master writes a one to it. When the SIG0 bit is set, an interrupt is sent to the local bus interrupter. The SIG0 bit is cleared when the local processor writes a one to the SIG0 bit in this register or the CSIG0 bit in the local interrupt clear register.
Page 185: Vmechip2 Board Status/Control Register
VMEchip2 Board Status/Control Register ADR/SIZ Local Bus: $FFF40104/VMEbus: $XXY2 (8 bits [5 used]) NAME OPER RESET 0 PSL 0 PSL This register is the VMEchip2 board status/control register. SYSFL SCON http://www.mcg.mot.com/literature This bit is cleared by an LM3 cycle on the VMEbus. This bit is set when the local processor or a VMEbus master writes a one to the LM3 bit in this register.
Page 186: General Purpose Register 0
VMEchip2 General Purpose Register 0 ADR/SIZ NAME OPER RESET This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. General Purpose Register 1 ADR/SIZ NAME...
Page 187: General Purpose Register 3
General Purpose Register 2 ADR/SIZ Local Bus: $FFF40110/VMEbus: $XXY8 (16 bits) NAME OPER RESET This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification.
Page 188: General Purpose Register 5
VMEchip2 General Purpose Register 4 ADR/SIZ NAME OPER RESET This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. General Purpose Register 5 ADR/SIZ NAME...
Page 189: Introduction
Introduction The Memory Controller ASIC (MC2 chip) is one of three ASICs that are part of the MVME172 hardware set. Summary of Major Features BBRAM and time-of-day clock (M48T58) interface with bus sizing. PROM interface with bus sizing. Flash interface with bus sizing.
Page 190: Functional Description
(J11, pins 7 and 8, GPI3) input to the initialization PAL. (The initialization device was discussed in the previous section.) This enables the MVME172 to execute reset code from either the PROM or Flash. The MC2 chip executes multiple cycles to the eight-bit Flash/PROM devices so that byte, word, or longword accesses are allowed.
Page 191: Bbram Interface
BBRAM Interface The MC2 chip provides a read/write interface to the BBRAM by any bus master on the MC68060 bus. The BBRAM interface operates identically to the Flash in that it performs dynamic sizing for accesses to the 8-bit BBRAM to make it appear contiguous. This feature allows code to be executable from the BBRAM.
Page 192: Mc68060-Bus Master Support For 82596Ca
MC2 Chip MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Command blocks. To execute an MPU Channel Attention, the MC68060-bus master performs a simple read or write to address $FFF46004. MC68060-Bus Master Support for 82596CA The 82596CA has DMA capability with an Intel i486-bus interface.
Page 193: Lanc Interrupt
100 ns devices. The size of the SRAM is initialized in the DRAM/SRAM Options Register when the MVME172 is reset. SRAM performance at 25 MHz is 5,3,3,3 for read and write cycle. SRAM performance at 33 MHz is 6,4,4,4 for read cycles and 6,3,3,3 for write cycles.
Page 194: Z85230 Scc Interface
Z85230 have priority over those from the second Z85230. The MC2 chip supports as many as four Z85230 devices. (There are two Z85230s on the MVME172. Refer to the Board Level Hardware Description in your MVME172 installation and use manual.) The Table 3-1. DRAM Performance...
Page 195: Tick Timers
addresses for the devices are defined as follows. Note that CSR bits were added to the General Control Register to control the delay time for the Z85230 IACK cycle. Address Range $FFF45000 - $FFF453FF $FFF45400 - $FFF457FF $FFF45800 - $FFF45BFF $FFF45C00 - $FFF45FFF Tick Timers The MC2 chip implements four 32-bit tick timers.
Page 196: Watchdog Timer
VMEbus. Local Bus Timer The MVME172 provides a time-out function for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The time-out value is selectable by software for 8 sec, 64 sec, 256 sec, or infinite.
Page 197: Table 3-2. Mc2 Chip Register Map
Tick Timer 4 Control Control SRAM Space Base Address Register SRAM Space Size Options Reserved LANC Interrupt Control General Purpose MVME172 Inputs Version D7-D0 Interrupt Vector Base Register Tick Timer 1 Control Tick Timer 1 Interrupt Control Tick Timer 3...
Page 198: Programming Model
MC2 Chip Table 3-2. MC2 Chip Register Map (Continued) Offset D31-D24 Bus Clock RESET Switch Control DRAM Control 32-bit Prescaler Count Register Programming Model This section defines the programming model for the control and status registers (CSR) in the MC2 chip. The base address of the CSR is $FFF42000.
Page 199: Mc2 Chip Id Register
MC2 Chip ID Register ADR/SIZ NAME OPER RESET 1 PL 0 PL ID7-ID0 MC2 Chip Revision Register ADR/SIZ NAME OPER RESET 0 PL 0 PL RV7-RV0 The current value of the chip revision is $01. This register http://www.mcg.mot.com/literature $FFF42000 (8 bits) 0 PL 0 PL 0 PL...
Page 200: General Control Register
ADR/SIZ NAME OPER RESET 0 PL FAST MIEN This bit is low for the MVME172 boards. Do not change it. If it is changed, the board will not operate properly. Caution 3-12 $FFF42000 (8 bits) SCCIT1 SCCIT0 0 PL 0 PL...
Page 201: Interrupt Vector Base Register
SCCIT<1:0>These bits define the IACK daisy chain time for the SCC These bits must be initialized to 01 for the MVME172 boards because they contain two Z85230 devices. Caution Interrupt Vector Base Register The interrupt vector base register is an 8-bit read/write register that is used to supply the vector to the MC68xx060 during interrupt acknowledge cycles.
Page 202: Table 3-3. Interrupt Vector Base Register Encoding And Priority
MC2 Chip The encoding for the interrupt sources is shown in the next table, where IV3-IV0 refer to bits 3-0 of the vector passed during the IACK cycle: The priority referenced in the following table is established in the MC2 chip logic by implementing a daisy chain request/grant network.
Page 203: Programming The Tick Timers
Programming the Tick Timers There are four programmable tick timers in the MC2 chip. These timers are identical in function to the timers implemented in the PCCchip2 and the VMEchip2. Tick Timer 1 and 2 Compare and Counter Registers The Tick Timer Counter is compared to the Compare Register. When they are equal, an interrupt is sent to the local bus interrupter and the overflow counter is incremented.
Page 204 MC2 Chip Tick Timer 1 Compare Register ADR/SIZ NAME OPER RESET Tick Timer 1 Counter ADR/SIZ NAME OPER RESET Tick Timer 2 Compare Register ADR/SIZ NAME OPER RESET 3-16 $FFF42004 (32 bits) . . . Tick Timer 1 Compare Register $FFF42008 (32 bits) .
Page 205: Lsb Prescaler Count Register
Tick Timer 2 Counter ADR/SIZ NAME OPER RESET LSB Prescaler Count Register This register is used to generate the 1 MHz clock for the four tick timers. This register is read-only. It increments to $ff at the processor frequency, then it is loaded from the Prescaler Clock Adjust Register. ADR/SIZ NAME OPER...
Page 206: Prescaler Clock Adjust Register
MC2 Chip Prescaler Clock Adjust Register This register adjusts the prescaler so that it maintains a 1 MHz clock source for the tick timers. To provide a 1 MHz clock, the prescaler adjust register should be programmed based on the following equation: Prescaler Clock Adjust Register = 256 - processor clock (MHz) For example, for operation at 20 MHz the prescaler value is $EC, at 25 MHz it is $E7, and at 33 MHz it is $DF.
Page 207 Tick Timer 2 Control Register ADR/SIZ NAME OVF3 OVF2 OPER RESET 0 PL 0 PL Tick Timer 1 Control Register ADR/SIZ NAME OVF3 OVF2 OPER RESET 0 PL 0 PL COVF OVF3-OVF0 http://www.mcg.mot.com/literature $FFF42014 (8 bits) OVF1 OVF0 0 PL 0 PL $FFF42014 (8 bits) OVF1...
Page 208: Tick Timer Interrupt Control Registers
MC2 Chip Tick Timer Interrupt Control Registers There are four tick timer interrupt control registers. The register format is the same for all four registers. Tick Timer 4 Interrupt Control Register ADR/SIZ NAME OPER RESET Tick Timer 3 Interrupt Control Register ADR/SIZ NAME OPER...
Page 209 Tick Timer 1 Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 ICLR http://www.mcg.mot.com/literature $FFF4201B (8 bits) ICLR 0 PL 0 PL 0 PL These three bits select the interrupt level for the tick timers. Level 0 does not generate an interrupt. Writing a logic 1 to this bit clears the tick timer interrupt (i.e., INT bit in this register).
Page 210: Dram Parity Error Interrupt Control Register
DRAM Parity Error Interrupt Control Register The DRAM Parity Error Interrupt Control Register controls the interrupt logic for parity error interrupts. In the MVME172, the parity control and interrupt logic is contained in the DRAM Parity Error Interrupt Control Register and the DRAM Control Register located at $FFF4201C and $FFF42048 respectively.
Page 211: Scc Interrupt Control Register
SCC Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 http://www.mcg.mot.com/literature $FFF4201C (8 bits) 0 PL 0 PL These three bits select the interrupt level for the SCC controller. Level 0 does not generate an interrupt. When this bit is set high, the interrupt is enabled. The interrupt is disabled when this bit is low.
Page 212: Tick Timer 3 And 4 Control Registers
MC2 Chip Tick Timer 3 and 4 Control Registers Tick Timer 4 Control Register ADR/SIZ NAME OVF3 OPER RESET 0 PL Tick Timer 3 Control Register ADR/SIZ NAME OVF3 OPER RESET 0 PL COVF OVF3-OVF0 3-24 $FFF4201C (8 bits) OVF2 OVF1 OVF0 0 PL...
Page 213: Dram And Sram Memory Controller Registers
DRAM space starts at address 0 and SRAM space starts at $FFE00000. DRAM and SRAM are inhibited by reset. Software can examine the MVME172 DRAM/SRAM Options Register at address $FFF42024 bits 20-16 to determine the size of the SRAM and DRAM.
Page 214: Sram Space Base Address Register
MC2 Chip SRAM Space Base Address Register ADR/SIZ NAME OPER RESET B31-B17 DRAM Space Size Register ADR/SIZ NAME OPER RESET 0 PL DZ2-DZ0 The size bits configure the non-ECC DRAM decoder for 3-26 $FFF42020 (16 bits) 15-1 B31-B17 $FFE0 PL B31 - B17 are compared to local bus address signals A31 - A17 for memory reference cycles.
Page 215: Dram/Sram Options Register
DZ2-DZ0 DZx bits indicate the size and architecture of the non-ECC SZ1-SZ0 http://www.mcg.mot.com/literature Table 3-4. DRAM Size Control Bit Encoding DZ2 - DZ0 Memory Size Not defined for MVME172 Not defined for MVME172 Not defined for MVME172 Not defined for MVME172 4 MByte (non-interleaved) 8 MByte (non-interleaved) DRAM is not present.
Page 216: Table 3-5. Dram Size Control Bit Encoding
MC2 Chip 3-28 Table 3-5. DRAM Size Control Bit Encoding DZ2 - DZ0 DRAM Configuration Not defined for MVME172 Not defined for MVME172 Not defined for MVME172 Not defined for MVME172 4 MByte (non-interleaved) 8 MByte (non-interleaved) DRAM is not present...
Page 217: Sram Space Size Register
0 PL SZ1-SZ0 Table 3-7. SRAM Size Control Bit Encoding Note For an MVME172 with 128 KB of SRAM, the software must program SZ1-SZ0 = $1 (512 KB). Therefore, the SRAM contents will repeat in the memory map. http://www.mcg.mot.com/literature $FFF42024 (8 bits) SRAM ENABLE must be set to a one before the SRAM can be accessed.
Page 218: Lanc Error Status Register
MC2 Chip LANC Error Status Register ADR/SIZ NAME OPER RESET SCLR LTO, EXT, PRTY 3-30 $FFF42028 (8 bits) PRTY 0 PL Writing a 1 to this bit clears bits LTO, EXT, and PRTY. Reading this bit always yields 0. These bits indicate the status of the last local bus error condition encountered by the LANC while performing DMA accesses to the local bus.
Page 219: 82596Ca Lanc Interrupt Control Register
82596CA LANC Interrupt Control Register ADR/SIZ NAME PLTY E/L* OPER RESET 0 PL 0 PL IL2-IL0 ICLR E/L* PLTY http://www.mcg.mot.com/literature $FFF42028 (8 bits) ICLR 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for the 82596CA LANC. Level 0 does not generate an interrupt.
Page 220: Lanc Bus Error Interrupt Control Register
MC2 Chip LANC Bus Error Interrupt Control Register ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 ICLR 3-32 $FFF42028 (8 bits) ICLR 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for the 82596CA LANC bus error condition.
Page 221: Scsi Error Status Register
SCSI Error Status Register ADR/SIZ NAME OPER RESET SCLR LTO, EXT, PRTY General Purpose Inputs Register The contents of a PAL and the state of an 8-position jumper block are translated to bit settings of the General Purpose Inputs Register, Version Register and DRAM/SRAM Options Register when the MC2 chip is reset.
Page 222 Application Specific V10 - V8 are general purpose inputs which are connected to three jumpers on the MVME172 board. If the bit is set to a one, the jumper is absent; if it is a zero, the jumper is present. The jumpers for V10 - V8 are located at J21 pins...
Page 223: Mvme172 Version Register
MVME172 Version Register The contents of a PAL and the state of an 8-position jumper block are translated to bit settings of the General Purpose Inputs Register, Version Register and DRAM/SRAM Options Register when the MC2 chip is reset. These registers are read only. Writes to these registers are terminated without exception but do not change their contents.
Page 224: Scsi Interrupt Control Register
MC2 Chip SCSI Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 3-36 V3 set to a one indicates that the Ethernet interface is not present. V3 set to a zero indicates that a Ethernet interface is present. V4 set to a one indicates that the MC68060 is present. V4 set to a zero indicates that an MC68LC060 is present.
Page 225: Tick Timer 3 And 4 Compare And Counter Registers
Tick Timer 3 and 4 Compare and Counter Registers Tick timers three and four are defined here because they maintain this relative position in the memory map. Refer to the sections on tick timer one and two in this chapter for a description of the tick timers. Tick Timer 3 Compare Register ADR/SIZ NAME...
Page 226: Bus Clock Register
MC2 Chip Tick Timer 4 Compare Register ADR/SIZ NAME OPER RESET Tick Timer 4 Counter ADR/SIZ NAME OPER RESET Bus Clock Register The Bus Clock Register should be programmed with the hexadecimal value of the operating clock frequency in MHz (i.e., $21 for 33 MHz). The MC2 chip uses the value programmed in this register to control the refresh timer so that the DRAMs are refreshed every 15.6 microseconds.
Page 227: Prom Access Time Control Register
BCK5-BCK0 The refresh rate is defined by the following equation: PROM Access Time Control Register The MVME172 is populated with a 150ns PROM memory device. Due to the wide range of PROM speeds, the contents can be changed by software to adjust for a specific speed.
Page 228: Flash Access Time Control Register
MC2 Chip ROM0 Flash Access Time Control Register The MVME172 is populated with a 120ns Flash memory device. Due to the wide range of Flash speeds, the contents can be changed by software to adjust for a specific speed. ADR/SIZ...
Page 229: Abort Switch Interrupt Control Register
ABORT Switch Interrupt Control Register The following table describes the ABORT switch interrupt logic in the MC2 chip. ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 ICLR http://www.mcg.mot.com/literature $FFF42040 (8 bits) ICLR 0 PL 0 PL 0 PL These three bits select the interrupt level for the ABORT switch.
Page 230: Reset Switch Control Register
RESET RSWE BDFLO CPURS PURS BRFLI 3-42 switch on the MVME172 front panel and several status and $FFF42044 (8 bits) BRFLI PURS 1 PL switch enable bit is used with the ‘‘no RESET VMEbus interface’’ option. This bit is duplicated at the same bit position in the VMEchip2 at location $FFF40060.
Page 231: Watchdog Timer Control Register
Watchdog Timer Control Register The watchdog timer control logic in the MC2 chip is used with the "No VMEbus Interface" option. This function is duplicated at the same bit locations in the VMEchip2 at location $FFF40060. The VMEchip2 has the additional option of selecting SYSRESET (i.e., VMEbus reset).
Page 232: Access And Watchdog Time Base Select Register
MC2 Chip Access and Watchdog Time Base Select Register The watchdog timer control logic in the MC2 chip is used with the "No VMEbus Interface" option. This function is duplicated at the same bit locations in the VMEchip2 at location $FFF4004C. It is permissible to enable the watchdog timer in both the VMEchip2 and the MC2 chip.
Page 233: Dram Control Register
DRAM Control Register This register controls the parity checking mode and DRAM enable for non-ECC applications. ADR/SIZ NAME OPER RESET RAMEN http://www.mcg.mot.com/literature signal is sent to the local bus. Note that the Version Register bit V1 must be set to a 1 to enable the MC2 chip access timer (i.e., it must be a "No VMEbus Interface"...
Page 234: Mpu Status Register
MC2 Chip PAREN-PARINT MPU Status Register This logic is duplicated in the VMEchip2 at location $FFF40048, bits 11, 10, 9, and 7. The duplication is to enable "No VMEbus Interface" operation. ADR/SIZ NAME OPER RESET 3-46 PAREN PARINT NONE INTERRUPT NONE CHECKED INTERRUPT CHECKED NONE means no parity checking.
Page 235 MLTO MLPE MLBE MCLR http://www.mcg.mot.com/literature When this bit is set, the MPU received a TEA and the status indicated a local bus time-out. This bit is cleared by a writing a one to the MCLR bit in this register. This bit is used with the "No VMEbus Interface"...
Page 236: 32-Bit Prescaler Count Register
$FFF4204C. This means that this register is located at the same address ($FFF40064) on an MVME172 with the VMEchip2 as well as an MVME172 without the VMEchip2. This feature is provided for those applications which require a Prescaler Count Register to run on all MVME172 versions.
Page 237: Introduction
Introduction This chapter describes the IndustryPack Interface Controller (IP2 chip) ASIC for the MC68060 bus. The IP2 chip interfaces to up to four IndustryPacks (IPs) to the MC68060. Summary of Major Features Provides all logic required to interface MC68060 bus to four IndustryPacks.
Page 238: Functional Description
MI* is negated, then the IP2 chip assumes that the cycle is over and that it is not to participate. The 200/300-Series MVME172 does not implement interfaces to IP_c and IP_d, although these interfaces are documented in Chapter 4 and the physical control registers for them exist.
Page 239: Local Bus To Industrypack Dma Controllers
Local Bus to IndustryPack DMA Controllers The IP2 supports two basic types of DMA cycles: “standard DMA” (sDMA) and “addressed DMA” (aDMA). sDMA cycles are requested by the IP. When the DMA controller (DMAC) detects a DMA request and if that DMA controller is enabled, it will acknowledge the request by transferring data between the local bus and the I/O space of the requesting IP device.
Page 240 DMA function is determined by the settings of jumper J26 (as is the state of the snoop control signals for all other DMA cycle types). Refer to the Hardware Preparation section of your MVME172 installation and use manual.
Page 241: Clocking Environments And Performance
Clocking Environments and Performance The IP2 chip has two clock domains. The majority of the logic is controlled by the MC68060 local bus clock which can be 25 MHz or 32 MHz. The IndustryPack interface is controlled by the IndustryPack clock. The IndustryPack clock can be 8 MHz or set equal to the local bus clock.
Page 242: Table 4-1. Ip2 Chip Clock Cycles
IP2 Chip Bus Frequency MC68060 25 MHz 32 MHz 32 MHz Notes 1. This column is a measure of IndustryPack bandwidth for Table 4-1. IP2 Chip Clock Cycles Period and Bandwidth to 32-Bit IP Space Back to Back Examine (Note 1) 8 MHz 4 IP clocks 8 MB/sec...
Page 243: Programmable Clock
Programmable Clock The IP2 chip implements a general purpose programmable clock output for external connection to the IndustryPacks. This feature complies with the STROBE function defined in the IndustryPack specification. The programmable clock’s clock source is the MC68060 bus clock. This clock input is fed through an 8-bit programmable pre-scaling counter whose output is fed to a 16-bit counter.
Page 244: Industrypack Error Reporting
IP2 Chip indicates that a local bus error did occur as a consequence of a DMA operation. The contents of the local bus address counter can be examined for the address that caused the bus error. IndustryPack Error Reporting Each IndustryPack interface has an error pin. The error status from the four interfaces are available in the General Control Registers.
Page 245: Overall Memory Map
Overall Memory Map The following memory map table includes all devices selected by the IP2 chip map decoder. Table 4-2. IP2 Chip Overall Memory Map Address Range Programmable IP_a/IP_ab Memory Space Programmable IP_b Memory Space Programmable IP_c/IP_cd Memory Space Programmable IP_d Memory Space $FFF58000-$FFF5807F IP_a I/O Space...
Page 246: Programming Model
IP2 Chip Programming Model This section defines the programming model for the control and status registers (CSRs) in the IP2 chip. The base address of the CSRs is hardwired to $FFFBC000. The possible operations for each bit in the CSR are as follows: The possible states of the bits after assertion of the RESET* pin (powerup reset or any local reset) are as defined below.
Page 247: Table 4-3. Ip2 Chip Memory Map - Control And Status Registers
Table 4-3. IP2 Chip Memory Map - Control and Status Registers IP2 Chip Base Address = $FFFBC000 Register Register Name Offset CHIP ID CHIP REVISION RESERVED VECTOR BASE IP_a MEM a_BASE31 a_BASE30 BASE UPPER IP_a MEM a_BASE23 a_BASE22 BASE LOWER IP_b MEM b_BASE31 b_BASE30...
Page 248 IP2 Chip Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued) IP2 Chip Base Address = $FFFBC000 Register Register Name Offset IP_b GENERAL b_ERR CONTROL IP_c GENERAL c_ERR CONTROL IP_d GENERAL d_ERR CONTROL RESERVED IP CLOCK ARBITRATION CONTROL IP RESET 4-12...
Page 249 Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued) IP2 Chip Base Address = $FFFBC000 Register Register Name Offset DMAC for IndustryPack a, request 0. This register set is referred to as DMACa in the text. DMA_a STATUS DMA_a INT CTRL...
Page 250 IP2 Chip Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued) IP2 Chip Base Address = $FFFBC000 Register Register Name Offset DMAC for IndustryPack b, request 0 or for IndustryPack a, request 1. This register set is referred to as DMACb in the text. DMA_b STATUS DMA_b INT...
Page 251 Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued) IP2 Chip Base Address = $FFFBC000 Register Register Name Offset DMAC for IndustryPack c, request 0. This register set is referred to as DMACc in the text. DMA_c STATUS DMA_c INT CTRL...
Page 252 IP2 Chip Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued) IP2 Chip Base Address = $FFFBC000 Register Register Name Offset DMAC for IndustryPack d, request 0 or for IndustryPack c, request 1, and for programmable CLOCK. This register set, not including the programmable Clock, is referred to as DMACd in the text.
Page 253: Chip Id Register
Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued) IP2 Chip Base Address = $FFFBC000 Register Register Name Offset Programmable Clock INT CON- TROL Programmable PLTY Clock GEN CONTROL Programmable Clock TIMER Programmable Clock TIMER Chip ID Register The read-only Chip ID Register is hard-wired to a hexadecimal value of $23.
Page 254: Vector Base Register
IP2 Chip ADR/SIZ NAME REV7 OPER RESET Vector Base Register ADR/SIZ NAME OPER RESET The interrupt Vector Base Register is an 8-bit read/write register that is used to supply the vector to the CPU during an interrupt acknowledge cycle for the four DMA controller interrupts and for the programmable clock interrupt.
Page 255: Ip_A, Ip_B, Ip_C, Ip_D Memory Base Address Registers
A normal read access to the Vector Base Register yields the value $0F if the read happens before it has been initialized. A normal read access yields all 0’s on bits 0-2, and the value that was last written on bits 3-7, if the read happens after the Vector Base Register was initialized.
Page 256: Ip_A Or Double Size Ip_Ab Memory Base Address Registers
IP2 Chip Note IP_a or Double Size IP_ab Memory Base Address Registers ADR/SIZ NAME($04) a_BASE31 NAME($05) a_BASE23 OPER RESET IP_b Memory Base Address Registers ADR/SIZ NAME($06) b_BASE31 b_BASE30 b_BASE29 b_BASE28 b_BASE27 b_BASE26 b_BASE25 b_BASE24 NAME($07) b_BASE23 b_BASE22 b_BASE21 b_BASE20 b_BASE19 b_BASE18 b_BASE17 b_BASE16 OPER RESET 4-20...
Page 257: Ip_C Or Double Size Ip_Cd Memory Base Address Registers
IP_c or Double Size IP_cd Memory Base Address Registers (Not used on 200/300-Series MVME172.) ADR/SIZ NAME($08) c_BASE31 c_BASE30 NAME($09) c_BASE23 c_BASE22 OPER RESET IP_d Memory Base Address Registers (Not used on 200/300-Series MVME172.) ADR/SIZ NAME($0A) d_BASE31 d_BASE30 d_BASE29 d_BASE28 d_BASE27 d_BASE26 d_BASE25 d_BASE24...
Page 258 IP2 Chip ADR/SIZ NAME($0C) a_SIZE23 NAME($0D) b_SIZE23 NAME($0E) c_SIZE23 NAME($0F) d_SIZE23 OPER RESET SIZE23-16 23 22 21 20 19 18 17 16 Note that 16MB is only possible using a double size IP. 4-22 $FFFBC00C through $FFFBC00F (8 bits each) a_SIZE22 a_SIZE21 a_SIZE20...
Page 259: Ip_A, Ip_B, Ip_C, And Ip_D; Irq0 And Irq1 Interrupt Control Registers
IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control Registers The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172 ADR/SIZ $FFFBC010 through $FFFBC017 (8 bits each) NAME($10) a0_PLTY a0_E/L* NAME($11) a1_PLTY a1_E/L* NAME($12)
Page 260: Ip_A, Ip_B, Ip_C, And Ip_D; General Control Registers
IP2 Chip PLTY IP_a, IP_b, IP_c, and IP_d; General Control Registers The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. ADR/SIZ NAME($18) a_ERR NAME($19) b_ERR NAME($1A) c_ERR NAME($1B) d_ERR OPER RESET 4-24 When this bit is low, interrupt is activated by a falling edge/low level of the IndustryPack IRQ*.
Page 261 Note The default BTD setting is to insert the additional one clock period delay between read cycles. WIDTH1, WIDTH0 http://www.mcg.mot.com/literature Setting BTD (bus turn around delay) to a one will insert one inactive clock period following a read cycle on the IP bus.
Page 262 IP2 Chip Note RT1, RT0 4-26 WIDTH1 WIDTH0 When programming b_WIDTH1-b_WIDTH0 for either 8- bits or 16-bits, a_WIDTH1-a_WIDTH0 must be programmed for one of 8-bits or 16-bits. This applies whether or not a_MEN is set. For example, if offset $19 is set to the value $09, then offset $18 can be set to $04, $05, $08, or $09, but not to $00, or $01.
Page 263 a_ERR b_ERR c_ERR d_ERR http://www.mcg.mot.com/literature Recovery Time with IP = 8 MHz 0 microseconds 2 microseconds 4 microseconds 8 microseconds back I/O and/or ID accesses are ensured if a single size access is followed by a single size access, or if a double size, longword access is followed by a single or double size access.
Page 264: Ip Clock Register
The IP32 bit controls clock synchronization logic. It does not change the clock frequency on the bus. Jumper J11 on the 200/300-Series MVME172, and Jumper J14 on the 400-/500-Series, control the IP bus clock source. If J11 (200/300-Series) or J14 (400/500-Series) pins 1 and 2 are jumpered, then the IP clock source is set to 8 MHz.
Page 265: Dma Arbitration Control Register
DMA Arbitration Control Register The DMA arbitration control register contents determine whether a fixed or fair arbitration algorithm is used to determine how the MC68060 local bus is attached to the internal DMA data paths. ADR/SIZ NAME OPER RESET ROTAT PRI1,PRI0 Priority with one DMA channel at IP sockets a, b, c, &...
Page 266: Ip Reset Register
RES bit, IPRESET* stays asserted until software clears RES. The MVME172 does not comply with the IP specification regarding reset. The MVME172 does not monitor Vcc and assert reset if Vcc is below a certain threshold. The IPRESET signal to the IP bus is asserted when the there is a cold power up reset.
Page 267: Programming The Dma Controllers
DMA function is determined by the settings of jumper J26 (as is the state of the snoop control signals for all other DMA cycle types). Refer to the Hardware Preparation section of your MVME172 installation and use manual. http://www.mcg.mot.com/literature...
Page 268 IP2 Chip Each DMAC’s control is divided into two registers. The first register is only accessible by the processor. The second register can be loaded by the processor in the direct mode and by the DMAC in the command chaining mode.
Page 269: Dma Enable Function
DMA Control Register 1 for a description of how the register sets are associated with the physical DMA request from the Industry Packs. The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. http://www.mcg.mot.com/literature Programming Model...
Page 270 IP2 Chip DMA Status Register ADR/SIZ NAME OPER RESET DONE IPTO DLBE CHANI 4-34 $FFFBC020, $38, $50, $68 (8 bits each) DLBE IPEND CHANI This bit is set when DMAC has finished executing commands and there were no errors, or DMAC has finished executing commands because the DHALT bit was set.
Page 271 IPEND DMA Interrupt Control Register The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. ADR/SIZ NAME OPER RESET DIL2-DIL0 DICLR DIEN DINT DMA Enable Register The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172.
Page 272 IP2 Chip ADR/SIZ OPER RESET 4-36 $FFFBC022, $3A, $52, $6A (8 bits each) Setting the DEN bit to a one will enable the DMA function. Software should not write to the DMA control registers between the time the DEN bit is set and the DMA process is completed.
Page 273 DMA Control Register 1 The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. ADR/SIZ NAME DHALT OPER RESET A_CH1, C_CH1 WIDTH1- WIDTH0 http://www.mcg.mot.com/literature $FFFBC024, $3C, $54, $6C (8 bits each) DTBL ADMA WIDTH1 This bit must remain cleared. If it is set to a one, the IP2 chip ASIC will not function correctly.
Page 274 IP2 Chip ADMA DTBL DHALT 4-38 bits in the General Control Registers, these width control bits define the width of both the memory and I/O interface. WIDTH1 WIDTH0 Assumed Data Bus Width Setting ADMA to a one will enable the address mode DMA operation.
Page 275 The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. ADR/SIZ NAME INTE...
Page 276 DMA Local Bus Address Counter In the direct mode, this counter is programmed with the starting address of the data in local bus memory. The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. ADR/SIZ NAME OPER...
Page 277 IndustryPack bus for different IndustryPack memory widths, described later in this chapter. The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. Note For sDMA operations, the IndustryPack Counter must be cleared before the DMAC is enabled.
Page 278 IP2 Chip The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. ADR/SIZ NAME OPER RESET DMA Table Address Counter In the command chaining mode, this counter should be loaded by the processor with the starting address of the list of commands. Note that the command packets in local bus memory must always be 16-byte aligned.
Page 279: Programming The Programmable Clock
Programming the Programmable Clock Programmable clock registers are defined in the following paragraphs. The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172. programmable Clock Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-0 ICLR http://www.mcg.mot.com/literature...
Page 280 IP2 Chip Programmable Clock General Control Register ADR/SIZ NAME PLTY OPER RESET PS2-0 4-44 $FFFBC081 (8 bits) These three bits select the frequency of the pre-scale logic output The MC68060 bus clock (BCK) is used as the input to the pre-scale logic. BCK is ether 25 MHz or 32 MHz. BCK frequency can be determined by examining the Version Register in the MC2 chip ASIC.
Page 281 PLTY Programmable Clock Timer Register ADR/SIZ NAME OPER RESET When enabled, the programmable clock timer counter increments until it matches the value contained in this register, at which time it rolls over and resumes counting. The effect is that the frequency of the programmable clock output is the frequency of the (pre-scaler output)/(the-value-in-this- register + 1).
Page 282: Local Bus To Industrypack Addressing
IP2 Chip Local Bus to IndustryPack Addressing The following sections provide examples that illustrate local bus versus IndustryPack addressing for different IndustryPack spaces and programmed port widths. Throughout the examples LBA refers to the local bus address defined by LA<23-0>, and IPA refers to the IndustryPack address.
Page 283: 16-Bit Memory Space
16-Bit Memory Space This example is for IP_a, where the IP_a memory space is programmed with a base address of $00000000, a size of 8MB, and a port width of 16 bits. The relationship of the IndustryPack address to the local bus address is: IPA=LBA.
Page 284: 32-Bit Memory Space
IP2 Chip 32-Bit Memory Space This example is for IP_ab, where the IP_ab memory space is programmed with a base address of $00000000, a size of 16MB, and a port width of 32 bits. The relationship of the IndustryPack address to the local bus address is: IPA<22-1>...
Page 285: Ip_A I/O Space
IP_a I/O Space This example is for IP_a I/O space. The relationship of the IndustryPack address to the local bus address is: IPA<6-0> = LBA<6-0>. Note that IPA<22-7> do not pertain to I/O space. $FFF58000 $FFF58001 $FFF58002 $FFF58003 $FFF5807C $FFF5807D $FFF5807E $FFF5807F http://www.mcg.mot.com/literature...
Page 286: Ip_Ab I/O Space
IP2 Chip IP_ab I/O Space This example is for 32-bit, IP_ab I/O space. The relationship of the IndustryPack address to the local bus address is: IPA<6-1> = LBA<7-2> and IPA<0> = LBA<0>. Note that IPA<22-7> do not pertain to I/O space. 4-50 IPA<6-0>...
Page 287: Ip_A Id Space
IP_a ID Space This example is for IP_a ID space. The relationship of the IndustryPack address to the local bus address is: IPA<5-0> = LBA<5-0>. Note that IPA<22-6> do not pertain to ID space. $FFF58080 $FFF58081 $FFF58082 $FFF58083 $FFF580BC $FFF580BD $FFF580BE $FFF580BF http://www.mcg.mot.com/literature...
Page 288: Ip To Local Bus Data Routing
IP2 Chip IP to Local Bus Data Routing This section shows data routing from an IP to the local bus. Memory Space Accesses The following table shows the data routing when accessing IP memory space. IPWIDTH refers to the memory space width that has been programmed into the general control register for the IndustryPack being accessed.
Page 289 IPWIDTH LBSIZE BYTE 8 Bits WORD LWORD BYTE 16 Bits WORD LWORD BYTE 32 Bits WORD LWORD http://www.mcg.mot.com/literature LD<31-24> LD<23-16> IPXD<7-0> IPXD<7-0> IPXD<7-0> IPXD<7-0> 1,3, IPXD<7-0> IPXD<7-0> IPXD<15-8> IPXD<7-0> IPXD<15-8> IPXD<7-0> IPXD<15-8> IPXD<7-0> IPBD<15-8> IPBD<7-0> IPBD<15-8> IPBD<7-0> IPBD<15-8> IPBD<7-0> IP to Local Bus Data Routing LD<15-8>...
Page 290: I/O And Id Space Accesses
IP2 Chip I/O and ID Space Accesses The following table shows the data routing when accessing IP I/O or ID space. SPACE refers to the IndustryPack space being accessed. LBSIZE refers to local bus transfer size. LBA refers to local bus address signals 1,0. IPA refers to IndustryPack address signals 2,1,0.
Page 291: Introduction
This chapter describes the ECC DRAM Controller ASIC (MCECC) used on the memory mezzanine boards with ECC protection. The MCECC is designed for the 200/300-Series MVME172 boards and is used in a set of two, to provide the interface to a 144-bit wide DRAM memory system.
Page 292: Functional Description
The MCECC is designed to be used as a set of two chips. A pair of MCECCs works with x4 DRAM memory chips to form a memory system for the MVME172 boards. A pair of MCECCs that is connected to implement a memory control function is referred to as an "MCECC pair".
Page 293: Table 5-1. Mcecc Specifications
Random, non-burst writes are the slowest kind of access because they require that the MCECC pair perform a read-modify-write cycle to the DRAM in order to complete. The MCECC pair responds to the local bus in two clocks during random writes, but then it takes another eight clocks for the DRAM read-modify-write cycle to complete, thereby making the effective cycle time 10 clocks if the following access by the local bus master is to DRAM.
Page 294: Ecc
MCECC When (SC1, SC0) do not indicate that snooping is inhibited, the MCECC pair responds differently to DRAM accesses, based on whether the cycle is a read or a write, and on the snoop wait (SWAIT) control bit. For a read with SWAIT = 0, the MCECC pair immediately starts a read cycle to the DRAM and latches the data from the DRAMs.
Page 295: Error Reporting
pair writes all 144 bits. When the local bus master requests a byte, word (two-byte), or longword write to DRAM, the MCECC pair performs a 144- bit wide read cycle to DRAM, merges the appropriate local bus write data in, and writes 144 bits to DRAM. Error Reporting The MCECCs generate the ECC check bits for write cycles.
Page 296: Triple (Or Greater) Bit Error (Cycle Type = Burst Read Or Non-Burst Read)
MCECC Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read) Some of these errors are detected correctly and are treated the same as a double bit error. The rest could show up as "no error" or "single bit error", both of which are incorrect.
Page 297: Double Bit Error (Cycle Type = Scrub)
Notify the local MPU via interrupt if so enabled. Double Bit Error (Cycle Type = Scrub) Do not perform the write portion of the cycle. This causes the location to continue to indicate non-correctable error when accessed. Log the error if one has not already been logged. Notify the local MPU via interrupt if so enabled.
Page 298: Refresh
MCECC occurs, the local bus master is notified if such interrupts are enabled in the control register. A software bit is available to disable the read portion of the scrub cycle. Refresh The MCECC pair provides refresh control for the DRAM. It performs a single CAS-before-RAS refresh cycle to the two DRAM blocks approximately once every 15.6 s.
Page 299: Programming Model
stream". The reset serial bit stream initializes the MCECC pair by setting or resetting the bits that appear in the Defaults 1 and Defaults 2 Registers. Software can override this initial setting by writing to the Defaults Registers. It is not recommended that non-test software alter the bits in the Defaults Registers.
Page 300: Table 5-2. Mcecc Internal Register Memory Map, Part 1
MCECC The possible states of the bits after local, software, and power-up reset are as defined below. A summary of the first eight CSR registers (the ones that correspond to those found in the MEMC040) is shown in even though there are two sets of these registers, one for the lower MCECC and one for the upper MCECC, software should only perform read and write cycles to the control and status registers in the upper MCECC.
Page 301 Table 5-2. MCECC Internal Register Memory Map, Part 1 MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) DUMMY 1 BASE BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 ADDRESS DRAM BAD23 BAD22 BAD21 BAD20 BAD19 BAD18 BAD17 BAD16 CONTROL BCLK BCK7 FREQUENCY A summary of the remaining CSR registers is shown in...
Page 302 MCECC Table 5-3. MCECC Internal Register Memory Map, Part 2 MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Offset Name DATA CONTROL SCRUB RACODE CONTROL SCRUB SBPD15 PERIOD SCRUB SBPD7 PERIOD CHIP CPS7 PRESCALE SCRUB SRDIS TIME ON/OFF SCRUB PRESCALE SCRUB...
Page 303 Table 5-3. MCECC Internal Register Memory Map, Part 2 (Continued) MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Offset Name SCRUB SAC15 ADDR CNTR SCRUB SAC7 ADDR CNTR ERROR ERRLOG LOGGER ERROR EA31 ADDRESS ERROR EA23 ADDRESS ERROR EA15 ADDRESS ERROR...
Page 304: Chip Id Register
MCECC Chip ID Register The Chip ID Register is hard-wired to a hexadecimal value of $81. The MCECC can be given a software reset by writing a value of $0F to this register. This write is terminated properly with TA*, and sets most internal registers to their default (power-up) state.
Page 305: Memory Configuration Register
Memory Configuration Register ADR/SIZ NAME OPER RESET MSIZ2-MSIZ0 MSIZ2 MSIZ1 MSIZ0 Memory Size Difference from MEMC040: NONE except that they reflect input pins on the MEMC040; while they reflect register bits that are initialized by the reset serial bit stream on the MCECC. http://www.mcg.mot.com/literature 1st $FFF43008/2nd $FFF43108 (8-bits) FSTRD...
Page 306: Dummy Register 0
Difference from MEMC040: bit = WPB (write-per-bit input strap status) for MEMC040; bit = 0 for MCECC (WPB = 0 on current versions of MVME172). Read Bit 4 is a read only bit that is always 1. Difference from MEMC040: bit = EXTPEN (external parity enable input strap status) for MEMC040;...
Page 307: Dummy Register 1
Dummy Register 1 Dummy Register 1 is hard-wired to all zeros. Writes to this register are ignored; however, the MCECC always terminates the cycles properly with TA*. Difference from MEMC040: register = Alternate Control for MEMC040; register = $00 for MCECC. ADR/SIZ NAME OPER...
Page 308: Dram Control Register
MCECC DRAM Control Register The bit assignments for the DRAM Control Register are: ADR/SIZ NAME BAD23 BAD22 RWB5 SWAIT RWB3 NCEIEN NCEBEN RAMEN OPER RESET 0 PLS RAMEN NCEBEN Setting the NCEBEN control bit enables the MCECC pair NCEIEN When NCEIEN is set, the logging of a non-correctable RWB3 5-18 1st $FFF43018/2nd $FFF43118 (8-bits)
Page 309 Difference from MEMC040: bit = WWP (write-wrong- parity) for MEMC040; bit = RWB (general purpose read write bit) for MCECC. SWAIT Difference from MEMC040: when bit set - no difference for snooping, when bit cleared - MEMC040 REV. 1 no difference, MEMC040 REV.
Page 310: Bclk Frequency Register
MCECC BAD22, BAD23 BCLK Frequency Register The Bus Clock (BCLK) Frequency Register should be programmed with the hexadecimal value of the operating clock frequency in MHz (i.e., $19 for 25 MHz and $21 for 33 MHz). The MCECC pair uses the value programmed in this register to control the Prescaler Counter.
Page 311: Data Control Register
Note None of the remaining registers have counterparts in the MEMC040 because they are associated with functions contained only in the MCECC pair. Data Control Register ADR/SIZ NAME OPER RESET RWCKB http://www.mcg.mot.com/literature 1st $FFF43020/2nd $FFF43120 (16-bits) DERC ZFILL RWCKB 1 PLS 0 PLS 0 PLS READ/WRITE CHECKBITS, when set, enables the data...
Page 312 MCECC 1. Stop all scrub operations by clearing all of the STON bits and setting 2. Set the DERC and RWCKB bits in the Data Control Register. 3. Perform the desired read and/or write checkbit operations. 4. Clear the DERC and RWCKB bits in the Data Control Register. 5.
Page 313: Scrub Control Register
Scrub Control Register ADR/SIZ NAME RACODE RADATA OPER RESET V PLS 0 PLS IDIS SBEIEN SCRBEN This control bit enables the scrubber to operate. When SCRB http://www.mcg.mot.com/literature 1st $FFF43024/2nd $FFF43124 (8-bits) HITDIS SCRB SCRBEN 0 V PLS 0 PLS 0 PLS When cleared, the Image DISable bit allows writes to the upper MCECC control registers to duplicate the data to the lower MCECC control registers.
Page 314: Scrub Period Register Bits 15-8
MCECC HITDIS RADATA This bit controls a function that is not currently used in the RACODE This bit controls a function that is not currently used in the Scrub Period Register Bits 15-8 The Scrub Period Control Register controls how often a scrub of the entire memory is performed if the SCRBEN bit is set in the Scrub Control Register.
Page 315: Chip Prescaler Counter
Chip Prescaler Counter This register reflects the current value in the prescaler counter. The Prescaler Counter is used with the BCLK Frequency Register to produce a 1 MHz clock signal for use by the refresher, and by the scrubber. The register is readable and writable for test purposes.
Page 316 MCECC STON2-STON0 5-26 STOFF2 STOFF1 STOFF0 Scrubber Time Off Request DRAM immediately Request DRAM after 16 BCLK cycles Request DRAM after 32 BCLK cycles Request DRAM after 64 BCLK cycles Request DRAM after 128 BCLK cycles Request DRAM after 256 BCLK cycles Request DRAM after 512 BCLK cycles...
Page 317: Scrub Prescaler Counter (Bits 21-16)
SRDIS Scrub Prescaler Counter (Bits 21-16) The Scrub Prescaler Counter uses the 1MHz clock as an input to create the .5 Hz clock that is used for the scrub period. Writes to this address update the scrub prescaler. Reads to this address yield the value in the scrub prescaler.
Page 318: Scrub Prescaler Counter (Bits 15-8)
MCECC Scrub Prescaler Counter (Bits 15-8) This register reflects the current value in the scrub prescaler bits 15-8. ADR/SIZ NAME SPS15 OPER RESET 0 PLS Scrub Prescaler Counter (Bits 7-0) This register reflects the current value in the scrub prescaler bits 7-0. ADR/SIZ NAME SPS7...
Page 319: Scrub Timer Counter (Bits 7-0)
ADR/SIZ NAME ST15 ST14 OPER RESET 0 PLS 0 PLS Scrub Timer Counter (Bits 7-0) This register reflects the current value in the Scrub Timer Counter bits 7-0. ADR/SIZ NAME OPER RESET 0 PLS 0 PLS Scrub Address Counter (Bits 26-24) This read/write register is the Scrub Address Counter.
Page 320: Scrub Address Counter (Bits 23-16)
MCECC ADR/SIZ NAME OPER RESET Scrub Address Counter (Bits 23-16) This register reflects the current value in the Scrub Address Counter bits 23-16. ADR/SIZ NAME SAC23 OPER RESET 0 PLS Scrub Address Counter (Bits 15-8) This register reflects the current value in the Scrub Address Counter bits 15-8.
Page 321: Scrub Address Counter (Bits 7-4)
Scrub Address Counter (Bits 7-4) This register reflects the current value in the Scrub Address Counter bits 7-4. ADR/SIZ NAME SAC7 SAC6 OPER RESET 0 PLS 0 PLS Error Logger Register ADR/SIZ NAME ERRL OPER RESET 0 PLS 0 PLS http://www.mcg.mot.com/literature 1st $FFF43058/2nd $FFF43158 (8-bits) SAC5...
Page 322: Error Address (Bits 31-24)
MCECC EALT ESCRB ERRLOG When set, ERRLOG indicates that a single or a double bit Error Address (Bits 31-24) This register reflects the value that was on bits 31-24 of the local MC68060 address bus at the last logging of an error. ADR/SIZ NAME EA31...
Page 323: Error Address (Bits 23-16)
Error Address (Bits 23-16) This register reflects the value that was on bits 23-16 of the local MC68060 address bus at the last logging of an error. ADR/SIZ NAME EA23 EA22 OPER RESET 0 PLS 0 PLS Error Address Bits (15-8) This register reflects the value that was on bits 15-8 of the local MC68060 address bus at the last logging of an error.
Page 324: Error Syndrome Register
MCECC Error Syndrome Register ADR/SIZ NAME OPER RESET 0 PLS S7-S0 Defaults Register 1 ADR/SIZ NAME WRHDIS OPER RESET 0 PL It is not recommended that non-test software write to this register. RSIZ2-RSIZ0 5-34 1st $FFF43070/2nd $FFF43170 (16-bits) 0 PLS 0 PLS 0 PLS 0 PLS...
Page 325 RSIZ2 SELI1, SELI0 SELI1 FSTRD http://www.mcg.mot.com/literature RSIZ1 RSIZ0 DRAM Array Size 4MB using one 144-bit wide block of 256Kx4 DRAMs 8MB using two 144-bit wide blocks of 256Kx4 DRAMs 16MB using one 144-bit wide block of 1Mx4 DRAMs 32MB using two 144-bit wide blocks of 1Mx4 DRAMs 64MB using one 144-bit wide block of 4Mx4 DRAMs...
Page 326: Defaults Register 2
MCECC STATCOL When the STATCOL bit is set, the RACODE and/or WRHDIS This bit controls a function that is not currently used in the Defaults Register 2 ADR/SIZ NAME FRC_OPEN XY_FLIP REFDIS TVECT NOCACHE RESST2 RESST1 RESST0 OPER R/W RESET 0 PLS It is not recommended that non-test software write to this register.
Page 327: Initialization
TVECT REFDIS XY_FLIP When XY_FLIP is set, the opposite internal set of cache FRC_OPN When FRC_OPN is set, the internal DRAM read latches Initialization Most DRAM vendors require that the DRAMs be subjected to some number of access cycles before the DRAMs are fully operational. The MCECC does not perform this automatically but depends on software to perform enough dummy accesses to DRAM to meet the requirement.
Page 328 MCECC operating at 25 MHz. This sequence may have to be altered to perform the scrub more slowly if the scrub causes the DRAM to consume too much power at full speed. 1. Make sure that the scrubber is disabled by clearing the SCRBEN bit 2.
Page 329: Syndrome Decode
Syndrome Decode A syndrome code value of $00 indicates no error found. All other syndrome code values indicate an error with the bit in error decoded as shown in the following table. Note that BANK A corresponds to A3,A2 = 00, BANK B to A3,A2 = 01, BANK C to A3,A2 = 10, and BANK D to A3,A2 = 11.
Page 330 MCECC Bank in Error BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C BANK C Bank in Error BANK B BANK B BANK B BA3K B...
Page 331 Bank in Error BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A Bank in Error UPPER/LOWER CHECKBITS UPPER/LOWER CHECKBITS UPPER/LOWER...
Page 332 MCECC 5-42 Computer Group Literature Center Web Site...
Page 333: Table A-1. Motorola Computer Group Documents
ARelated Documentation Motorola Computer Group Documents The Motorola publications listed below are applicable to the MVME172. To obtain paper or electronic copies of the documents listed or of other publications not shipped with this product (such as interconnect signal information, parts lists, and schematics for the MVME172), you can...
Page 334: Appendix A Related Documentation
If any supplements have been issued for a printed manual or guide, they will be furnished along with that document. Motorola Computer Group publication numbers are suffixed with characters which represent the revision level of the document, such as “/IH2”...
Page 335 Table A-2. Manufacturers’ Documents (Continued) Document Title and Source 82596CA Local Area Network Coprocessor data sheet 82596 User’s Manual Intel Corporation, Literature Sales, P.O. Box 58130, Santa Clara, CA 95052-8130 NCR 53C710 SCSI I/O Processor, data manual document NCR Corporation, Microelectronics Products Division, Colorado Springs, CO MK48T58(B) Timekeeper and 8Kx8 Zeropower RAMs Databook...
Page 336 Related Documentation...
Page 337: Introduction
Introduction This appendix demonstrates how to use interrupts on the MVME172. It gives an example of how to generate and handle a VMEchip2 Tick Timer 1 interrupt on an MVME172 that has a VMEbus connection. Specific values have been given for the register writes.
Page 338 VMEchip2 Tick Timer 1 Periodic Interrupt Example Periodic Tick Timer 1 interrupts now occur, so you need an interrupt handler. Section 3 gives the details, as follows. Step Register and Address Tick Timer 1 Control Register $FFF40060 (8 bits) Set up local bus interrupter: Step Register and Address Vector Base Register...
Page 339 Set up an interrupt handler routine: Step Your interrupt handler should include the following features. http://www.mcg.mot.com/literature Using Interrupts on the MVME172 Action and Reference Be sure the MC68060 vector base register is set up. Set the proper MC68060 exception vector location so the processor vectors to your interrupt handler location.
Page 340 VMEchip2 Tick Timer 1 Periodic Interrupt Example Computer Group Literature Center Web Site...
Page 341: Index
Numerics 32-bit Prescaler Count Register 53C710 SCSI controller interface 82596CA LAN interface 82596CA LANC Interrupt Control Register 3-31 A16/D16 space 2-6, 2-37 A16/D32 space 2-6, 2-37 A24/D16 space 2-6, 2-37, 2-51 A32/D16 space 2-6, 2-37, 2-51 ABORT Switch Interrupt Control Register 3-41 ABORT switch interrupt, address AC fail interrupter...
Page 342 block diagram 200/300-Series 400/500-Series VMEchip2 block diagrams block transfer cycles 2-11 mode modes, DMAC 2-59 board documentation address, GCSR 2-48 Control Register 2-71, failure 2-71 1-44 Status/Control Register, VMEchip2 2-107 BRDFAIL signal pin 2-71, broadcast interrupt function broadcast mode 2-16 BSY signal 2-17 Bus Clock Register...
Page 343 DMA continued Interrupt Control Register, IP2 chip Local Bus Address Counter, IP2 chip 4-40 Status Register, IP2 chip 4-34 Table Address Counter, IP2 chip transfers 2-12 DMAC byte counter 2-61 command packets 2-53 Control Register 1 (bits 0-7) 2-56 Control Register 2 (bits 0-7) 2-59 Control Register 2 (bits 8-15) interrupter...
Page 344 1-57 extended access cycles 2-34, fair mode, VMEchip2 2-8, features IP2 chip MC2 chip MCECC MVME172 VMEchip2 Flash Access Time Control Register Flash memory device Flash/EPROM interface functional blocks, VMEchip2 functional description IP2 chip MC2 chip...
Page 345 2-16 edge-sensitive 2-75 hardware-vectored 1-47 how to use IP2 chip masked 2-97 introduction interrupts, MVME172 IP2 chip MC2 chip MCECC chip MVME172 VMEchip2 IP Clock Register, IP2 chip 4-28 IP RESET Register, IP2 chip 4-30 IP to local bus data routing 4-52 http://www.mcg.mot.com/literature...
Page 346 local bus accesses 1-47 address counter, DMAC address range 2-39 base address, GCSR interrupt filters 2-99 interrupter 2-12 interrupter summary interrupter, how to set up interrupter, programming interrupter, VMEchip2 map decoder registers master 2-9, 2-10 memory map memory map, 200/300-Series memory map, 400/500-Series reset 2-107...
Page 347 Status Register VMEchip2 and MPU TEA, cause unidentified MVIP IndustryPack interfaces MVME172 features functional description introduction MVME172 Version Register MVME712x transition boards no address increment DMA transfers non-ECC DRAM controller non-privileged access cycles 2-34, 1-14 Non-Volatile RAM (NVRAM) 1-18 no-VMEbus option...
Page 348 periodic interrupt example power monitor 2-17 powerup reset VMEchip2 2-71 Prescaler Clock Adjust Register Prescaler Control Register Prescaler Counter 2-74 prescaler, VMEchip2 2-14 Priority (PRI) mode 2-17 priority interrupt 1-47 processor-to-VMEbus transfers program access cycles 2-33, program address modifier code Programmable Clock General Control Register, IP2 chip Interrupt Control Register, IP2 chip...
Page 349 Scrub Prescaler Counter (Bits 15-8) 5-28 (Bits 21-16) 5-27 (Bits 7-0) 5-28 Scrub Time On/Time Off Register Scrub Timer Counter (Bits 15-8) 5-28 (Bits 7-0) 5-29 SCSI bus interface controller interface Error Status Register 3-33 1-44 Interrupt Control Register 3-36 LTO error 1-56 memory map...
Page 350 tick timer interrupters 2-19 periodic interrupt example Tick Timer 1 and 2 Compare and Counter Registers Control Registers 3-18 Tick Timer 1 Compare Register 2-69, Control Register 2-74, Counter 2-69, 3-16 Interrupt Control Register Tick Timer 2 Compare Register 2-70, Control Register 2-73, Counter 2-70, 3-17...
Page 351 VMEbus requester, DMAC 2-13 VMEbus slave VMEbus Slave Address Modifier Select Register 1 Address Modifier Select Register 2 Address Translation Address Offset Register 1 2-29 Address Translation Address Offset Register 2 2-31 Address Translation Select Register 1 2-30 Address Translation Select Register 2 2-31 Ending Address Register 1 2-28...
Page 352 IN-12 Computer Group Literature Center Web Site Index...
Page 353 ® ™ 3/16” & 1/4” spine 86 - 100 pages ® ™ 5/16” spine 102 - 180 pages ® ™ 3/8” - 1/2” spine 182 - 308 pages MVME172 Programmer’s Reference Guide 5/8” - 1 1/8” spine 2 lines allowed...

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Motorola MVME172 Programmer's Reference Manual

CHAPTER 1 Board Description and Memory Maps

CHAPTER 2 Vmechip2

CHAPTER 3 MC2 Chip

CHAPTER 4 IP2 Chip

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Summary of Contents for Motorola MVME172